part6.hier_info

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

|part6
CLK => CLK~0.IN1
SW_A => SW_A~0.IN1
Address[0] => Address_in~4.DATAB
Address[1] => Address_in~3.DATAB
Address[2] => Address_in~2.DATAB
Address[3] => Address_in~1.DATAB
Address[4] => Address_in~0.DATAB
Data[0] => Data[0]~7.IN2
Data[1] => Data[1]~6.IN2
Data[2] => Data[2]~5.IN2
Data[3] => Data[3]~4.IN2
Data[4] => Data[4]~3.IN2
Data[5] => Data[5]~2.IN2
Data[6] => Data[6]~1.IN2
Data[7] => Data[7]~0.IN2
Wren => WrenC~0.IN1
Wren => always1~0.IN1
Wren => LED.DATAIN
LED <= Wren.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[0] <= SEG_COM~27.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[1] <= SEG_COM~26.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[2] <= SEG_COM~25.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[3] <= SEG_COM~24.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[4] <= SEG_COM~23.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[5] <= SEG_COM~22.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[6] <= SEG_COM~21.DB_MAX_OUTPUT_PORT_TYPE
SEG_COM[7] <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[0] <= SEG_DATA~63.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[1] <= SEG_DATA~62.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[2] <= SEG_DATA~61.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[3] <= SEG_DATA~60.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[4] <= SEG_DATA~59.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[5] <= SEG_DATA~58.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[6] <= SEG_DATA~57.DB_MAX_OUTPUT_PORT_TYPE
SEG_DATA[7] <= SEG_DATA~56.DB_MAX_OUTPUT_PORT_TYPE


|part6|count:Cnt
CLK => y~0.IN1
Reset => y~1.IN1
Q[0] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE


|part6|myram:Ram
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|part6|myram:Ram|altsyncram:altsyncram_component
wren_a => altsyncram_bvj1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_bvj1:auto_generated.data_a[0]
data_a[1] => altsyncram_bvj1:auto_generated.data_a[1]
data_a[2] => altsyncram_bvj1:auto_generated.data_a[2]
data_a[3] => altsyncram_bvj1:auto_generated.data_a[3]
data_a[4] => altsyncram_bvj1:auto_generated.data_a[4]
data_a[5] => altsyncram_bvj1:auto_generated.data_a[5]
data_a[6] => altsyncram_bvj1:auto_generated.data_a[6]
data_a[7] => altsyncram_bvj1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_bvj1:auto_generated.address_a[0]
address_a[1] => altsyncram_bvj1:auto_generated.address_a[1]
address_a[2] => altsyncram_bvj1:auto_generated.address_a[2]
address_a[3] => altsyncram_bvj1:auto_generated.address_a[3]
address_a[4] => altsyncram_bvj1:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_bvj1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_bvj1:auto_generated.q_a[0]
q_a[1] <= altsyncram_bvj1:auto_generated.q_a[1]
q_a[2] <= altsyncram_bvj1:auto_generated.q_a[2]
q_a[3] <= altsyncram_bvj1:auto_generated.q_a[3]
q_a[4] <= altsyncram_bvj1:auto_generated.q_a[4]
q_a[5] <= altsyncram_bvj1:auto_generated.q_a[5]
q_a[6] <= altsyncram_bvj1:auto_generated.q_a[6]
q_a[7] <= altsyncram_bvj1:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|part6|myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated
address_a[0] => altsyncram_jbf2:altsyncram1.address_a[0]
address_a[1] => altsyncram_jbf2:altsyncram1.address_a[1]
address_a[2] => altsyncram_jbf2:altsyncram1.address_a[2]
address_a[3] => altsyncram_jbf2:altsyncram1.address_a[3]
address_a[4] => altsyncram_jbf2:altsyncram1.address_a[4]
clock0 => altsyncram_jbf2:altsyncram1.clock0
data_a[0] => altsyncram_jbf2:altsyncram1.data_a[0]
data_a[1] => altsyncram_jbf2:altsyncram1.data_a[1]
data_a[2] => altsyncram_jbf2:altsyncram1.data_a[2]
data_a[3] => altsyncram_jbf2:altsyncram1.data_a[3]
data_a[4] => altsyncram_jbf2:altsyncram1.data_a[4]
data_a[5] => altsyncram_jbf2:altsyncram1.data_a[5]
data_a[6] => altsyncram_jbf2:altsyncram1.data_a[6]
data_a[7] => altsyncram_jbf2:altsyncram1.data_a[7]
q_a[0] <= altsyncram_jbf2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_jbf2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_jbf2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_jbf2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_jbf2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_jbf2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_jbf2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_jbf2:altsyncram1.q_a[7]
wren_a => altsyncram_jbf2:altsyncram1.wren_a


|part6|myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1
address_a[0] => altsyncram_p592:altsyncram3.address_a[1]
address_a[1] => altsyncram_p592:altsyncram3.address_a[2]
address_a[2] => altsyncram_p592:altsyncram3.address_a[3]
address_a[3] => altsyncram_p592:altsyncram3.address_a[4]
address_a[4] => altsyncram_p592:altsyncram3.address_a[5]
address_b[0] => altsyncram_p592:altsyncram3.address_b[1]
address_b[1] => altsyncram_p592:altsyncram3.address_b[2]
address_b[2] => altsyncram_p592:altsyncram3.address_b[3]
address_b[3] => altsyncram_p592:altsyncram3.address_b[4]
address_b[4] => altsyncram_p592:altsyncram3.address_b[5]
clock0 => altsyncram_p592:altsyncram3.clock0
clock1 => altsyncram_p592:altsyncram3.clock1
data_a[0] => altsyncram_p592:altsyncram3.data_a[0]
data_a[1] => altsyncram_p592:altsyncram3.data_a[1]
data_a[2] => altsyncram_p592:altsyncram3.data_a[2]
data_a[3] => altsyncram_p592:altsyncram3.data_a[3]
data_a[4] => altsyncram_p592:altsyncram3.data_a[4]
data_a[5] => altsyncram_p592:altsyncram3.data_a[5]
data_a[6] => altsyncram_p592:altsyncram3.data_a[6]
data_a[7] => altsyncram_p592:altsyncram3.data_a[7]
data_b[0] => altsyncram_p592:altsyncram3.data_b[0]
data_b[1] => altsyncram_p592:altsyncram3.data_b[1]
data_b[2] => altsyncram_p592:altsyncram3.data_b[2]
data_b[3] => altsyncram_p592:altsyncram3.data_b[3]
data_b[4] => altsyncram_p592:altsyncram3.data_b[4]
data_b[5] => altsyncram_p592:altsyncram3.data_b[5]
data_b[6] => altsyncram_p592:altsyncram3.data_b[6]
data_b[7] => altsyncram_p592:altsyncram3.data_b[7]
q_a[0] <= altsyncram_p592:altsyncram3.q_a[0]
q_a[1] <= altsyncram_p592:altsyncram3.q_a[1]
q_a[2] <= altsyncram_p592:altsyncram3.q_a[2]
q_a[3] <= altsyncram_p592:altsyncram3.q_a[3]
q_a[4] <= altsyncram_p592:altsyncram3.q_a[4]
q_a[5] <= altsyncram_p592:altsyncram3.q_a[5]
q_a[6] <= altsyncram_p592:altsyncram3.q_a[6]
q_a[7] <= altsyncram_p592:altsyncram3.q_a[7]
q_b[0] <= altsyncram_p592:altsyncram3.q_b[0]
q_b[1] <= altsyncram_p592:altsyncram3.q_b[1]
q_b[2] <= altsyncram_p592:altsyncram3.q_b[2]
q_b[3] <= altsyncram_p592:altsyncram3.q_b[3]
q_b[4] <= altsyncram_p592:altsyncram3.q_b[4]
q_b[5] <= altsyncram_p592:altsyncram3.q_b[5]
q_b[6] <= altsyncram_p592:altsyncram3.q_b[6]
q_b[7] <= altsyncram_p592:altsyncram3.q_b[7]
wren_a => altsyncram_p592:altsyncram3.wren_a
wren_b => altsyncram_p592:altsyncram3.wren_b


|part6|myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3
address_a[0] => ram_block4a0.PORTAADDR
address_a[0] => ram_block4a1.PORTAADDR
address_a[0] => ram_block4a2.PORTAADDR
address_a[0] => ram_block4a3.PORTAADDR
address_a[0] => ram_block4a4.PORTAADDR
address_a[0] => ram_block4a5.PORTAADDR
address_a[0] => ram_block4a6.PORTAADDR
address_a[0] => ram_block4a7.PORTAADDR
address_a[1] => ram_block4a0.PORTAADDR1
address_a[1] => ram_block4a1.PORTAADDR1
address_a[1] => ram_block4a2.PORTAADDR1
address_a[1] => ram_block4a3.PORTAADDR1
address_a[1] => ram_block4a4.PORTAADDR1
address_a[1] => ram_block4a5.PORTAADDR1
address_a[1] => ram_block4a6.PORTAADDR1
address_a[1] => ram_block4a7.PORTAADDR1
address_a[2] => ram_block4a0.PORTAADDR2
address_a[2] => ram_block4a1.PORTAADDR2
address_a[2] => ram_block4a2.PORTAADDR2
address_a[2] => ram_block4a3.PORTAADDR2
address_a[2] => ram_block4a4.PORTAADDR2
address_a[2] => ram_block4a5.PORTAADDR2
address_a[2] => ram_block4a6.PORTAADDR2
address_a[2] => ram_block4a7.PORTAADDR2
address_a[3] => ram_block4a0.PORTAADDR3
address_a[3] => ram_block4a1.PORTAADDR3
address_a[3] => ram_block4a2.PORTAADDR3
address_a[3] => ram_block4a3.PORTAADDR3
address_a[3] => ram_block4a4.PORTAADDR3
address_a[3] => ram_block4a5.PORTAADDR3
address_a[3] => ram_block4a6.PORTAADDR3
address_a[3] => ram_block4a7.PORTAADDR3
address_a[4] => ram_block4a0.PORTAADDR4
address_a[4] => ram_block4a1.PORTAADDR4
address_a[4] => ram_block4a2.PORTAADDR4
address_a[4] => ram_block4a3.PORTAADDR4
address_a[4] => ram_block4a4.PORTAADDR4
address_a[4] => ram_block4a5.PORTAADDR4
address_a[4] => ram_block4a6.PORTAADDR4
address_a[4] => ram_block4a7.PORTAADDR4
address_a[5] => ram_block4a0.PORTAADDR5
address_a[5] => ram_block4a1.PORTAADDR5
address_a[5] => ram_block4a2.PORTAADDR5
address_a[5] => ram_block4a3.PORTAADDR5
address_a[5] => ram_block4a4.PORTAADDR5
address_a[5] => ram_block4a5.PORTAADDR5
address_a[5] => ram_block4a6.PORTAADDR5
address_a[5] => ram_block4a7.PORTAADDR5
address_b[0] => ram_block4a0.PORTBADDR
address_b[0] => ram_block4a1.PORTBADDR
address_b[0] => ram_block4a2.PORTBADDR
address_b[0] => ram_block4a3.PORTBADDR
address_b[0] => ram_block4a4.PORTBADDR
address_b[0] => ram_block4a5.PORTBADDR
address_b[0] => ram_block4a6.PORTBADDR
address_b[0] => ram_block4a7.PORTBADDR
address_b[1] => ram_block4a0.PORTBADDR1
address_b[1] => ram_block4a1.PORTBADDR1
address_b[1] => ram_block4a2.PORTBADDR1
address_b[1] => ram_block4a3.PORTBADDR1
address_b[1] => ram_block4a4.PORTBADDR1
address_b[1] => ram_block4a5.PORTBADDR1
address_b[1] => ram_block4a6.PORTBADDR1
address_b[1] => ram_block4a7.PORTBADDR1
address_b[2] => ram_block4a0.PORTBADDR2
address_b[2] => ram_block4a1.PORTBADDR2
address_b[2] => ram_block4a2.PORTBADDR2
address_b[2] => ram_block4a3.PORTBADDR2
address_b[2] => ram_block4a4.PORTBADDR2
address_b[2] => ram_block4a5.PORTBADDR2
address_b[2] => ram_block4a6.PORTBADDR2
address_b[2] => ram_block4a7.PORTBADDR2
address_b[3] => ram_block4a0.PORTBADDR3
address_b[3] => ram_block4a1.PORTBADDR3
address_b[3] => ram_block4a2.PORTBADDR3
address_b[3] => ram_block4a3.PORTBADDR3
address_b[3] => ram_block4a4.PORTBADDR3
address_b[3] => ram_block4a5.PORTBADDR3
address_b[3] => ram_block4a6.PORTBADDR3
address_b[3] => ram_block4a7.PORTBADDR3
address_b[4] => ram_block4a0.PORTBADDR4
address_b[4] => ram_block4a1.PORTBADDR4
address_b[4] => ram_block4a2.PORTBADDR4
address_b[4] => ram_block4a3.PORTBADDR4
address_b[4] => ram_block4a4.PORTBADDR4
address_b[4] => ram_block4a5.PORTBADDR4
address_b[4] => ram_block4a6.PORTBADDR4
address_b[4] => ram_block4a7.PORTBADDR4
address_b[5] => ram_block4a0.PORTBADDR5
address_b[5] => ram_block4a1.PORTBADDR5
address_b[5] => ram_block4a2.PORTBADDR5
address_b[5] => ram_block4a3.PORTBADDR5
address_b[5] => ram_block4a4.PORTBADDR5
address_b[5] => ram_block4a5.PORTBADDR5
address_b[5] => ram_block4a6.PORTBADDR5
address_b[5] => ram_block4a7.PORTBADDR5
clock0 => ram_block4a0.CLK0
clock0 => ram_block4a1.CLK0
clock0 => ram_block4a2.CLK0
clock0 => ram_block4a3.CLK0
clock0 => ram_block4a4.CLK0
clock0 => ram_block4a5.CLK0
clock0 => ram_block4a6.CLK0
clock0 => ram_block4a7.CLK0
clock1 => ram_block4a0.CLK1
clock1 => ram_block4a1.CLK1
clock1 => ram_block4a2.CLK1
clock1 => ram_block4a3.CLK1
clock1 => ram_block4a4.CLK1
clock1 => ram_block4a5.CLK1
clock1 => ram_block4a6.CLK1
clock1 => ram_block4a7.CLK1
data_a[0] => ram_block4a0.PORTADATAIN
data_a[1] => ram_block4a1.PORTADATAIN
data_a[2] => ram_block4a2.PORTADATAIN
data_a[3] => ram_block4a3.PORTADATAIN
data_a[4] => ram_block4a4.PORTADATAIN
data_a[5] => ram_block4a5.PORTADATAIN
data_a[6] => ram_block4a6.PORTADATAIN
data_a[7] => ram_block4a7.PORTADATAIN
data_b[0] => ram_block4a0.PORTBDATAIN
data_b[1] => ram_block4a1.PORTBDATAIN
data_b[2] => ram_block4a2.PORTBDATAIN
data_b[3] => ram_block4a3.PORTBDATAIN
data_b[4] => ram_block4a4.PORTBDATAIN
data_b[5] => ram_block4a5.PORTBDATAIN
data_b[6] => ram_block4a6.PORTBDATAIN
data_b[7] => ram_block4a7.PORTBDATAIN
q_a[0] <= ram_block4a0.PORTADATAOUT
q_a[1] <= ram_block4a1.PORTADATAOUT
q_a[2] <= ram_block4a2.PORTADATAOUT
q_a[3] <= ram_block4a3.PORTADATAOUT
q_a[4] <= ram_block4a4.PORTADATAOUT
q_a[5] <= ram_block4a5.PORTADATAOUT
q_a[6] <= ram_block4a6.PORTADATAOUT
q_a[7] <= ram_block4a7.PORTADATAOUT
q_b[0] <= ram_block4a0.PORTBDATAOUT
q_b[1] <= ram_block4a1.PORTBDATAOUT
q_b[2] <= ram_block4a2.PORTBDATAOUT
q_b[3] <= ram_block4a3.PORTBDATAOUT
q_b[4] <= ram_block4a4.PORTBDATAOUT
q_b[5] <= ram_block4a5.PORTBDATAOUT
q_b[6] <= ram_block4a6.PORTBDATAOUT
q_b[7] <= ram_block4a7.PORTBDATAOUT
wren_a => ram_block4a0.PORTAWE