part6.map.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jbf2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jbf2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jbf2 " "Info: Found entity 1: altsyncram_jbf2" {  } { { "db/altsyncram_jbf2.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_jbf2.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jbf2 myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1 " "Info: Elaborating entity \"altsyncram_jbf2\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\"" {  } { { "db/altsyncram_bvj1.tdf" "altsyncram1" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_bvj1.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_p592.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_p592.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_p592 " "Info: Found entity 1: altsyncram_p592" {  } { { "db/altsyncram_p592.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_p592 myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3 " "Info: Elaborating entity \"altsyncram_p592\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|altsyncram_jbf2:altsyncram1\|altsyncram_p592:altsyncram3\"" {  } { { "db/altsyncram_jbf2.tdf" "altsyncram3" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_jbf2.tdf" 40 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_bvj1.tdf" "mgl_prim2" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_bvj1.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_bvj1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_bvj1.tdf" 37 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 00000000 " "Info: Parameter \"CVALUE\" = \"00000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1380011264 " "Info: Parameter \"NODE_NAME\" = \"1380011264\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 32 " "Info: Parameter \"NUMWORDS\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 4 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 8 " "Info: Parameter \"WIDTH_WORD\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 5 " "Info: Parameter \"WIDTHAD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "db/altsyncram_bvj1.tdf" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_bvj1.tdf" 37 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 631 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:D1 " "Info: Elaborating entity \"display\" for hierarchy \"display:D1\"" {  } { { "part6.v" "D1" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 0 Ram 8 5 " "Warning (12020): Port \"ordered port 0\" on the entity instantiation of \"Ram\" is connected to a signal of width 8. The formal width of the signal in the module is 5.  The extra bits will be ignored." {  } { { "part6.v" "Ram" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 42 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  The extra bits will be ignored." 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_DATA\[7\] GND " "Warning (13410): Pin \"SEG_DATA\[7\]\" is stuck at GND" {  } { { "part6.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part6/part6.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "5 5 " "Info: 5 registers lost all their fanouts during netlist optimizations. The first 5 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "count:Cnt\|y~14 " "Info: Register \"count:Cnt\|y~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "count:Cnt\|y~15 " "Info: Register \"count:Cnt\|y~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "count:Cnt\|y~16 " "Info: Register \"count:Cnt\|y~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "count:Cnt\|y~17 " "Info: Register \"count:Cnt\|y~17\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "count:Cnt\|y~18 " "Info: Register \"count:Cnt\|y~18\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Sophy/Desktop/LAB_8/part6/part6.map.smsg " "Info: Generated suppressed messages file C:/Users/Sophy/Desktop/LAB_8/part6/part6.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "400 " "Info: Implemented 400 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "354 " "Info: Implemented 354 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "212 " "Info: Peak virtual memory: 212 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 15 12:01:07 2009 " "Info: Processing ended: Fri May 15 12:01:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Info: Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}