part6.fit.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|irf_reg\[1\]\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|irf_reg\[1\]\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|shadow_irf_reg~265 " "Info: Destination node sld_hub:sld_hub_inst\|shadow_irf_reg~265" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|shadow_irf_reg~265 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~201 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~201" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 65 -1 0 } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~201 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~29 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg~29" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 704 -1 0 } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg~29 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~5 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~5" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process_0~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 823 -1 0 } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|irf_reg[1][0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~5  " "Info: Automatically promoted node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~5 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process_0~5 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|shadow_irf_reg~270 " "Info: Destination node sld_hub:sld_hub_inst\|shadow_irf_reg~270" {  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|shadow_irf_reg~270 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~96 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~96" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process_0~96 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~2 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~2" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process_0~2 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~97 " "Info: Destination node myram:Ram\|altsyncram:altsyncram_component\|altsyncram_bvj1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process_0~97" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|process_0~97 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "../../../../../altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 823 -1 0 } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|irf_reg[1][3] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}