part6.map.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

; Number of registers using Clock Enable       ; 69    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|tdo               ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |part6|myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |part6|myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0] ;
; 24:1               ; 4 bits    ; 64 LEs        ; 44 LEs               ; 20 LEs                 ; Yes        ; |part6|myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]      ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |part6|sld_hub:sld_hub_inst|hub_mode_reg[2]                                                                                                                                  ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |part6|sld_hub:sld_hub_inst|irf_reg[1][0]                                                                                                                                    ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |part6|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]                                                                                                          ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |part6|sld_hub:sld_hub_inst|irsr_reg[2]                                                                                                                                      ;
; 6:1                ; 5 bits    ; 20 LEs        ; 5 LEs                ; 15 LEs                 ; Yes        ; |part6|sld_hub:sld_hub_inst|shadow_irf_reg[1][0]                                                                                                                             ;
; 20:1               ; 4 bits    ; 52 LEs        ; 32 LEs               ; 20 LEs                 ; Yes        ; |part6|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1 ;
+---------------------------------+--------------------+------+---------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                            ;
+---------------------------------+--------------------+------+---------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                             ;
+---------------------------------+--------------------+------+---------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                        ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                         ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; Assignment           ; Value ; From ; To                                                                                                                                     ;
+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                                                                                                                                      ;
+----------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst           ;
+------------------------------+-------+------+---------+
; Assignment                   ; Value ; From ; To      ;
+------------------------------+-------+------+---------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -       ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -       ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; clr_reg ;
; POWER_UP_LEVEL               ; LOW   ; -    ; clr_reg ;
+------------------------------+-------+------+---------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
+----------------------+-------+------+-------------------------------+


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: myram:Ram|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+----------------------------+
; Parameter Name                     ; Value                ; Type                       ;
+------------------------------------+----------------------+----------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                    ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE             ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                    ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                    ;
; WIDTH_A                            ; 8                    ; Signed Integer             ;
; WIDTHAD_A                          ; 5                    ; Signed Integer             ;
; NUMWORDS_A                         ; 32                   ; Signed Integer             ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                    ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                    ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                    ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                    ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                    ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                    ;
; WIDTH_B                            ; 1                    ; Untyped                    ;
; WIDTHAD_B                          ; 1                    ; Untyped                    ;
; NUMWORDS_B                         ; 1                    ; Untyped                    ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                    ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                    ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                    ;