part6.map.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

; Remove Duplicate Registers                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                 ; Off                ; Off                ;
; Optimization Technique                                         ; Balanced           ; Balanced           ;
; Carry Chain Length                                             ; 70                 ; 70                 ;
; Auto Carry Chains                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                          ; Off                ; Off                ;
; Perform gate-level register retiming                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax         ; On                 ; On                 ;
; Auto ROM Replacement                                           ; On                 ; On                 ;
; Auto RAM Replacement                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                  ; On                 ; On                 ;
; Strict RAM Replacement                                         ; Off                ; Off                ;
; Allow Synchronous Control Signals                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                              ; Off                ; Off                ;
; Auto Resource Sharing                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                  ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing            ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                             ; Off                ; Off                ;
; Synchronization Register Chain Length                          ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report       ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report      ; 100                ; 100                ;
; Clock MUX Protection                                           ; On                 ; On                 ;
; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+----------------------+--------------------------+
; Name                 ; Setting                  ;
+----------------------+--------------------------+
; CYCLONEII_SAFE_WRITE ; RESTRUCTURE              ;
+----------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                     ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------------+
; part6.v                          ; yes             ; User Verilog HDL File            ; C:/Users/Sophy/Desktop/LAB_8/part6/part6.v                         ;
; myram.mif                        ; yes             ; User Memory Initialization File  ; C:/Users/Sophy/Desktop/LAB_8/part6/myram.mif                       ;
; altsyncram.tdf                   ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/lpm_decode.inc        ;
; aglobal81.inc                    ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/aglobal81.inc         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Megafunction                     ; c:/altera/81/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_bvj1.tdf           ; yes             ; Auto-Generated Megafunction      ; C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_bvj1.tdf          ;
; db/altsyncram_jbf2.tdf           ; yes             ; Auto-Generated Megafunction      ; C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_jbf2.tdf          ;
; db/altsyncram_p592.tdf           ; yes             ; Auto-Generated Megafunction      ; C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf          ;
; sld_mod_ram_rom.vhd              ; yes             ; Encrypted Megafunction           ; c:/altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd   ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction           ; c:/altera/81/quartus/libraries/megafunctions/sld_rom_sr.vhd        ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction           ; c:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd           ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Estimated Total logic elements              ; 297                      ;
;                                             ;                          ;
; Total combinational functions               ; 297                      ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 151                      ;
;     -- 3 input functions                    ; 70                       ;
;     -- <=2 input functions                  ; 76                       ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 262                      ;
;     -- arithmetic mode                      ; 35                       ;
;                                             ;                          ;
; Total registers                             ; 152                      ;
;     -- Dedicated logic registers            ; 152                      ;
;     -- I/O registers                        ; 0                        ;
;                                             ;                          ;
; I/O pins                                    ; 37                       ;
; Total memory bits                           ; 512                      ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO ;
; Maximum fan-out                             ; 126                      ;