part6.map.rpt

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Analysis & Synthesis report for part6
Fri May 15 12:01:07 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. State Machine - |part6|count:Cnt|y
 10. Registers Removed During Synthesis
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1
 15. Source assignments for myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3
 16. Source assignments for myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 17. Source assignments for sld_hub:sld_hub_inst
 18. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg
 19. Parameter Settings for User Entity Instance: myram:Ram|altsyncram:altsyncram_component
 20. Parameter Settings for User Entity Instance: myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|sld_mod_ram_rom:mgl_prim2
 21. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 22. In-System Memory Content Editor Settings
 23. Analysis & Synthesis Messages
 24. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri May 15 12:01:07 2009   ;
; Quartus II Version                 ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name                      ; part6                                   ;
; Top-level Entity Name              ; part6                                   ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 297                                     ;
;     Total combinational functions  ; 297                                     ;
;     Dedicated logic registers      ; 152                                     ;
; Total registers                    ; 152                                     ;
; Total pins                         ; 37                                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 512                                     ;
; Embedded Multiplier 9-bit elements ; 0                                       ;
; Total PLLs                         ; 0                                       ;
+------------------------------------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                            ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option                                                         ; Setting            ; Default Value      ;
+----------------------------------------------------------------+--------------------+--------------------+
; Device                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                          ; part6              ; part6              ;
; Family name                                                    ; Cyclone II         ; Stratix            ;
; Type of Retiming Performed During Resynthesis                  ; Full               ;                    ;
; Resynthesis Optimization Effort                                ; Normal             ;                    ;
; Physical Synthesis Level for Resynthesis                       ; Normal             ;                    ;
; Use Generated Physical Constraints File                        ; On                 ;                    ;
; Use smart compilation                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation            ; 1                  ; 1                  ;
; Restructure Multiplexers                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                            ; Off                ; Off                ;
; Preserve fewer node names                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                      ; Off                ; Off                ;
; Verilog Version                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                       ; Auto               ; Auto               ;
; Safe State Machine                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                              ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                     ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                 ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                        ; On                 ; On                 ;
; Parallel Synthesis                                             ; Off                ; Off                ;
; DSP Block Balancing                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                             ; On                 ; On                 ;
; Power-Up Don't Care                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                   ; Off                ; Off                ;