part6.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

wire \SEG_DATA~3495_combout ;
wire \SEG_DATA~3473_combout ;
wire \SEG_DATA~3477_combout ;
wire \SEG_DATA~3476_combout ;
wire \SEG_DATA~3478_combout ;
wire \D1|out[4]~1074_combout ;
wire \SEG_DATA~3479_combout ;
wire \SEG_DATA~3475_combout ;
wire \SEG_DATA~3497_combout ;
wire \SEG_DATA~3498_combout ;
wire \SEG_DATA~3486_combout ;
wire \SEG_DATA~3496_combout ;
wire \SEG_DATA~3481_combout ;
wire \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[6] ;
wire \SEG_DATA~3483_combout ;
wire \SEG_DATA~3484_combout ;
wire \SEG_DATA~3485_combout ;
wire \SEG_DATA~3487_combout ;
wire \D5|out[6]~814_combout ;
wire \SEG_DATA~3489_combout ;
wire \SEG_DATA~3488_combout ;
wire \SEG_DATA~3490_combout ;
wire \SEG_DATA~3492_combout ;
wire \SEG_DATA~3493_combout ;
wire \altera_reserved_tms~combout ;
wire \altera_internal_jtag~TDO ;

wire \ALT_INV_Equal2~135_combout ;
wire \ALT_INV_SEG_DATA~3456_combout ;
wire \ALT_INV_SEG_COM~95_combout ;
wire \ALT_INV_Equal2~136_combout ;
wire \ALT_INV_Equal2~137_combout ;
wire \ALT_INV_Equal2~138_combout ;
wire \ALT_INV_Equal2~139_combout ;
wire \ALT_INV_Equal2~140_combout ;
wire \ALT_INV_altera_internal_jtag~TMSUTAP ;
wire \ALT_INV_altera_internal_jtag~TCKUTAPclkctrl_outclk ;
wire \sld_hub_inst|shadow_jsm|ALT_INV_state[0]~clkctrl_outclk ;
wire [143:0] \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus ;
wire [143:0] \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus ;

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[0]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [0]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[0] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[1]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [1]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[1] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[2]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [2]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[2] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[3]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [3]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[3] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[4]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [4]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[4] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[5]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [5]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[5] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[6]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [6]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[6] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[7]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [7]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[7] ));


AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[0]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [0]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[0] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[1]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [1]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[1] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[2]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [2]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[2] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[3]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [3]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[3] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[4]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [4]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[4] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[5]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [5]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[5] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[6]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [6]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[6] ));

AND1 \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[7]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [7]),
	.Y(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b[7] ));


INV \INV_INST_Equal2~135_combout  (
	.IN1(\Equal2~135_combout ),
	.Y(\ALT_INV_Equal2~135_combout ));

INV \INV_INST_SEG_DATA~3456_combout  (
	.IN1(\SEG_DATA~3456_combout ),
	.Y(\ALT_INV_SEG_DATA~3456_combout ));

INV \INV_INST_SEG_COM~95_combout  (
	.IN1(\SEG_COM~95_combout ),
	.Y(\ALT_INV_SEG_COM~95_combout ));

INV \INV_INST_Equal2~136_combout  (
	.IN1(\Equal2~136_combout ),
	.Y(\ALT_INV_Equal2~136_combout ));

INV \INV_INST_Equal2~137_combout  (
	.IN1(\Equal2~137_combout ),
	.Y(\ALT_INV_Equal2~137_combout ));

INV \INV_INST_Equal2~138_combout  (
	.IN1(\Equal2~138_combout ),
	.Y(\ALT_INV_Equal2~138_combout ));

INV \INV_INST_Equal2~139_combout  (
	.IN1(\Equal2~139_combout ),
	.Y(\ALT_INV_Equal2~139_combout ));

INV \INV_INST_Equal2~140_combout  (
	.IN1(\Equal2~140_combout ),
	.Y(\ALT_INV_Equal2~140_combout ));

INV \INV_INST_altera_internal_jtag~TMSUTAP  (
	.IN1(\altera_internal_jtag~TMSUTAP ),
	.Y(\ALT_INV_altera_internal_jtag~TMSUTAP ));

INV \INV_INST_altera_internal_jtag~TCKUTAPclkctrl_outclk  (
	.IN1(\altera_internal_jtag~TCKUTAPclkctrl_outclk ),
	.Y(\ALT_INV_altera_internal_jtag~TCKUTAPclkctrl_outclk ));

INV \sld_hub_inst|shadow_jsm|INV_INST_state[0]~clkctrl_outclk  (
	.IN1(\sld_hub_inst|shadow_jsm|state[0]~clkctrl_outclk ),
	.Y(\sld_hub_inst|shadow_jsm|ALT_INV_state[0]~clkctrl_outclk ));

// atom is at M4K_X52_Y20
cycloneii_ram_block \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 (
	.portawe(\WrenC~combout ),
	.portaaddrstall(gnd),
	.portbrewe(\Ram|altsyncram_component|auto_generated|mgl_prim2|enable_write~9_combout ),
	.portbaddrstall(gnd),
	.clk0(\CLK~clkctrl_outclk ),
	.clk1(\altera_internal_jtag~TCKUTAPclkctrl_outclk ),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\Data[7]~combout ,\Data[6]~combout ,\Data[5]~combout ,\Data[4]~combout ,\Data[3]~combout ,\Data[2]~combout ,
\Data[1]~combout ,\Data[0]~combout }),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\Address_in[4]~224_combout ,\Address_in[3]~223_combout ,\Address_in[2]~222_combout ,\Address_in[1]~221_combout ,\Address_in[0]~220_combout ,\~GND~combout }),
	.portabyteenamasks(16'b1111111111111111),
	.portbdatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5]~regout ,
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[4]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[3]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[2]~regout ,
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[1]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0]~regout }),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3]~regout ,
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~regout ,\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~regout ,\~GND~combout }),
	.portbbyteenamasks(16'b1111111111111111),
	.modesel(49'b0011000111000100000000000001001001000000000000100),
	.portadataout(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus ),
	.portbdataout(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus ));
// synopsys translate_off
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .data_interleave_offset_in_bits = 1;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .data_interleave_width_in_bits = 1;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .init_file = "myram.mif";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .init_file_layout = "port_a";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .logical_ram_name = "myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ALTSYNCRAM";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .mixed_port_feed_through_mode = "dont_care";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .operation_mode = "bidir_dual_port";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_address_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_address_width = 6;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_byte_enable_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_byte_enable_clock = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_in_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_out_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_out_clock = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_first_address = 0;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_first_bit_number = 0;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_last_address = 63;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_logical_ram_depth = 64;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_logical_ram_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_write_enable_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_address_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_address_clock = "clock1";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_address_width = 6;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_byte_enable_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_in_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_in_clock = "clock1";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_out_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_out_clock = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_first_address = 0;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_first_bit_number = 0;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_last_address = 63;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_logical_ram_depth = 64;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_logical_ram_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_read_enable_write_enable_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_read_enable_write_enable_clock = "clock1";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .ram_block_type = "M4K";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .safe_write = "err_on_2clk";
// defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .mem_init0 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000;
// synopsys translate_on

// atom is at LCFF_X45_Y20_N7
cycloneii_lcell_ff \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3] (
	.clk(\altera_internal_jtag~TCKUTAPclkctrl_outclk ),
	.datain(\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~52_combout ),
	.sdata(gnd),
	.aclr(\sld_hub_inst|irf_reg[1][3]~clkctrl_outclk ),
	.sclr(\Ram|altsyncram_component|auto_generated|mgl_prim2|Equal1~33_combout ),
	.sload(gnd),
	.ena(vcc),
	.regout(\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~regout ));

// atom is at LCCOMB_X50_Y18_N2
cycloneii_lcell_comb \Add1~132 (
// Equation(s):
// \Add1~132_combout  = \cnt[0]~regout  $ VCC
// \Add1~133  = CARRY(\cnt[0]~regout )

	.dataa(vcc),
	.datab(\cnt[0]~regout ),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.modesel(4'b1011),
	.combout(\Add1~132_combout ),
	.cout(\Add1~133 ),
	.pathsel(8'b01001010));
// synopsys translate_off
// defparam \Add1~132 .lut_mask = 16'h33CC;
// defparam \Add1~132 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X50_Y18_N4
cycloneii_lcell_comb \Add1~134 (
// Equation(s):
// \Add1~134_combout  = \temp1[1]~regout  & !\Add1~133  # !\temp1[1]~regout  & (\Add1~133  # GND)
// \Add1~135  = CARRY(!\Add1~133  # !\temp1[1]~regout )

	.dataa(\temp1[1]~regout ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add1~133 ),
	.modesel(4'b0111),
	.combout(\Add1~134_combout ),
	.cout(\Add1~135 ),
	.pathsel(8'b10111001));
// synopsys translate_off
// defparam \Add1~134 .lut_mask = 16'h5A5F;
// defparam \Add1~134 .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X50_Y18_N6
cycloneii_lcell_comb \Add1~136 (
// Equation(s):
// \Add1~136_combout  = \Clock1~regout  & (\Add1~135  $ GND) # !\Clock1~regout  & !\Add1~135  & VCC
// \Add1~137  = CARRY(\Clock1~regout  & !\Add1~135 )

	.dataa(vcc),
	.datab(\Clock1~regout ),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add1~135 ),
	.modesel(4'b0111),
	.combout(\Add1~136_combout ),
	.cout(\Add1~137 ),
	.pathsel(8'b11011010));
// synopsys translate_off
// defparam \Add1~136 .lut_mask = 16'hC30C;
// defparam \Add1~136 .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X50_Y18_N8
cycloneii_lcell_comb \Add1~138 (