part6.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"

// DATE "05/15/2009 12:02:03"

// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This Verilog file should be used for PrimeTime (Verilog) only
// 

`timescale 1 ps/ 1 ps

module part6 (
	altera_reserved_tms,
	altera_reserved_tck,
	altera_reserved_tdi,
	altera_reserved_tdo,
	CLK,
	SW_A,
	Address,
	Data,
	Wren,
	LED,
	SEG_COM,
	SEG_DATA);
input 	altera_reserved_tms;
input 	altera_reserved_tck;
input 	altera_reserved_tdi;
output 	altera_reserved_tdo;
input 	CLK;
input 	SW_A;
input 	[4:0] Address;
input 	[7:0] Data;
input 	Wren;
output 	LED;
output 	[7:0] SEG_COM;
output 	[7:0] SEG_DATA;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("part6_v.sdo");
// synopsys translate_on

wire \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a[3] ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~regout ;
wire \Add1~132_combout ;
wire \Add1~134_combout ;
wire \Add1~137 ;
wire \Add1~139 ;
wire \Add1~138_combout ;
wire \Add1~141 ;
wire \Add1~140_combout ;
wire \Add1~143 ;
wire \Add1~142_combout ;
wire \Add1~145 ;
wire \Add1~144_combout ;
wire \Add1~147 ;
wire \Add1~146_combout ;
wire \Add1~149 ;
wire \Add1~148_combout ;
wire \Add1~151 ;
wire \Add1~150_combout ;
wire \Add1~152_combout ;
wire \Add2~133 ;
wire \Add2~132_combout ;
wire \Add2~135 ;
wire \Add2~134_combout ;
wire \Add2~137 ;
wire \Add2~136_combout ;
wire \Add2~139 ;
wire \Add2~138_combout ;
wire \Add2~141 ;
wire \Add2~140_combout ;
wire \Add2~143 ;
wire \Add2~142_combout ;
wire \Add2~145 ;
wire \Add2~144_combout ;
wire \Add2~147 ;
wire \Add2~146_combout ;
wire \Add2~149 ;
wire \Add2~148_combout ;
wire \Add2~151 ;
wire \Add2~150_combout ;
wire \Add2~152_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~51 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~52_combout ;
wire \Cnt|WideOr3~97_combout ;
wire \Cnt|WideOr1~98_combout ;
wire \D4|out[0]~522_combout ;
wire \SEG_DATA~3462_combout ;
wire \SEG_DATA~3464_combout ;
wire \D3|out[2]~444_combout ;
wire \D1|out[2]~1072_combout ;
wire \SEG_DATA~3468_combout ;
wire \D4|out[3]~524_combout ;
wire \SEG_DATA~3474_combout ;
wire \SEG_DATA~3480_combout ;
wire \SEG_DATA~3482_combout ;
wire \D4|out[6]~525_combout ;
wire \D1|out[6]~1075_combout ;
wire \SEG_DATA~3491_combout ;
wire \Clock~regout ;
wire \WrenC~combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1717_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1719_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1720_combout ;
wire \temp1[7]~regout ;
wire \temp1[6]~regout ;
wire \temp1[5]~regout ;
wire \temp1[4]~regout ;
wire \temp1[3]~regout ;
wire \temp1[1]~regout ;
wire \temp1[8]~regout ;
wire \temp1[9]~regout ;
wire \Equal0~140_combout ;
wire \temp1[10]~regout ;
wire \Equal0~141_combout ;
wire \Equal0~142_combout ;
wire \Equal0~143_combout ;
wire \temp2[5]~regout ;
wire \temp2[4]~regout ;
wire \temp2[3]~regout ;
wire \temp2[2]~regout ;
wire \temp2[1]~regout ;
wire \temp2[0]~regout ;
wire \temp2[6]~regout ;
wire \temp2[8]~regout ;
wire \temp2[7]~regout ;
wire \temp2[9]~regout ;
wire \Equal1~140_combout ;
wire \temp2[10]~regout ;
wire \Equal1~141_combout ;
wire \Equal1~142_combout ;
wire \Clock~18_combout ;
wire \temp1~283_combout ;
wire \temp1~284_combout ;
wire \temp1~285_combout ;
wire \temp1~286_combout ;
wire \temp1~287_combout ;
wire \temp1~288_combout ;
wire \temp2~316_combout ;
wire \temp2~317_combout ;
wire \temp2~318_combout ;
wire \temp2~319_combout ;
wire \temp2~320_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3]~regout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1728_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1729_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1730_combout ;
wire \D1|out[1]~1070_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[0]~regout ;
wire \sld_hub_inst|hub_info_reg|word_counter[2]~regout ;
wire \sld_hub_inst|hub_info_reg|word_counter[3]~regout ;
wire \sld_hub_inst|hub_info_reg|word_counter[4]~regout ;
wire \sld_hub_inst|hub_info_reg|word_counter[1]~regout ;
wire \sld_hub_inst|hub_info_reg|word_counter[0]~247 ;
wire \sld_hub_inst|hub_info_reg|word_counter[0]~246_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[1]~251 ;
wire \sld_hub_inst|hub_info_reg|word_counter[1]~250_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[2]~253 ;
wire \sld_hub_inst|hub_info_reg|word_counter[2]~252_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[3]~255 ;
wire \sld_hub_inst|hub_info_reg|word_counter[3]~254_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[4]~256_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR[0]~regout ;
wire \sld_hub_inst|irsr_reg[3]~517_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][4]~regout ;
wire \sld_hub_inst|node_ena~685_combout ;
wire \sld_hub_inst|hub_info_reg|clear_signal~combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~840_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR[1]~regout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~841_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~842_combout ;
wire \sld_hub_inst|irsr_reg[3]~525_combout ;
wire \sld_hub_inst|shadow_irf_reg~271_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~843_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[0]~248_combout ;
wire \sld_hub_inst|hub_info_reg|word_counter[0]~249_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR[2]~regout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~844_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~845_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR[3]~regout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~846_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~847_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~848_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~849_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR[0]~850_combout ;
wire \sld_hub_inst|hub_info_reg|WORD_SR~851_combout ;
wire \sld_hub_inst|shadow_jsm|state[0]~_wirecell_combout ;
wire \Clock~clkctrl_outclk ;
wire \Wren~combout ;
wire \cnt[0]~12_combout ;
wire \cnt[0]~regout ;
wire \cnt[1]~11_combout ;
wire \cnt[1]~regout ;
wire \cnt[2]~10_combout ;
wire \cnt[2]~regout ;
wire \Equal2~135_combout ;
wire \SEG_DATA~3456_combout ;
wire \SEG_COM~95_combout ;
wire \Equal2~136_combout ;
wire \Equal2~137_combout ;
wire \Equal2~138_combout ;
wire \Equal2~139_combout ;
wire \Equal2~140_combout ;
wire \Cnt|y.00001~6_combout ;
wire \SW_A~combout ;
wire \Cnt|y.00001~regout ;
wire \Cnt|y.00010~feeder_combout ;
wire \Cnt|y.00010~regout ;
wire \Cnt|y.00011~regout ;
wire \Cnt|y.00100~regout ;
wire \Cnt|y.00101~feeder_combout ;
wire \Cnt|y.00101~regout ;
wire \Cnt|y.00110~feeder_combout ;
wire \Cnt|y.00110~regout ;
wire \Cnt|y.00111~regout ;
wire \Cnt|y.01000~regout ;
wire \Cnt|y.01001~regout ;
wire \Cnt|y.01010~regout ;
wire \Cnt|y.01011~feeder_combout ;
wire \Cnt|y.01011~regout ;
wire \Cnt|y.01100~regout ;
wire \Cnt|y.01101~regout ;
wire \Cnt|y.01110~regout ;
wire \Cnt|y.01111~regout ;
wire \Cnt|y.10000~regout ;
wire \Cnt|y.10001~feeder_combout ;
wire \Cnt|y.10001~regout ;
wire \Cnt|y.10010~feeder_combout ;
wire \Cnt|y.10010~regout ;
wire \Cnt|y.10011~regout ;
wire \Cnt|y.10100~regout ;
wire \Cnt|y.10101~regout ;
wire \Cnt|y.10110~regout ;
wire \Cnt|y.10111~regout ;
wire \Cnt|y.11000~feeder_combout ;
wire \Cnt|y.11000~regout ;
wire \Cnt|y.11001~feeder_combout ;
wire \Cnt|y.11001~regout ;
wire \Cnt|y.11010~regout ;
wire \Cnt|y.11011~feeder_combout ;
wire \Cnt|y.11011~regout ;
wire \Cnt|y.11100~feeder_combout ;
wire \Cnt|y.11100~regout ;
wire \Cnt|y.11101~regout ;
wire \Cnt|y.11110~feeder_combout ;
wire \Cnt|y.11110~regout ;
wire \Cnt|y.11111~regout ;
wire \Cnt|y.00000~6_combout ;
wire \Cnt|y.00000~regout ;
wire \Cnt|WideOr3~96_combout ;
wire \Cnt|WideOr4~85_combout ;
wire \Cnt|WideOr3~98_combout ;
wire \Cnt|WideOr3~99_combout ;
wire \Cnt|WideOr1~99_combout ;
wire \Cnt|WideOr1~100_combout ;
wire \Cnt|WideOr1~101_combout ;
wire \Cnt|WideOr1~102_combout ;
wire \Cnt|WideOr4~86_combout ;
wire \Cnt|WideOr4~84_combout ;
wire \Cnt|WideOr4~87_combout ;
wire \D5|out[0]~811_combout ;
wire \Data[1]~combout ;
wire \Data[2]~combout ;
wire \Data[3]~combout ;
wire \D3|out[0]~443_combout ;
wire \altera_reserved_tck~combout ;
wire \altera_reserved_tdi~combout ;
wire \sld_hub_inst|tdo_bypass_reg~17_combout ;
wire \sld_hub_inst|tdo_bypass_reg~regout ;
wire \altera_internal_jtag~TMSUTAP ;
wire \sld_hub_inst|irf_proc~39_combout ;
wire \sld_hub_inst|shadow_jsm|state[8]~regout ;