part6.fit.rpt

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Fitter report for part6
Fri May 15 12:01:35 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Incremental Compilation Preservation Summary
  5. Incremental Compilation Partition Settings
  6. Incremental Compilation Placement Preservation
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Fitter Partition Statistics
 10. Input Pins
 11. Output Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Fitter RAM Summary
 22. Interconnect Usage Summary
 23. LAB Logic Elements
 24. LAB-wide Signals
 25. LAB Signals Sourced
 26. LAB Signals Sourced Out
 27. LAB Distinct Inputs
 28. Fitter Device Options
 29. Operating Settings and Conditions
 30. Estimated Delay Added for Hold Timing
 31. Advanced Data - General
 32. Advanced Data - Placement Preparation
 33. Advanced Data - Placement
 34. Advanced Data - Routing
 35. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Fri May 15 12:01:35 2009   ;
; Quartus II Version                 ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name                      ; part6                                   ;
; Top-level Entity Name              ; part6                                   ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C35F672C6                            ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 327 / 33,216 ( < 1 % )                  ;
;     Total combinational functions  ; 297 / 33,216 ( < 1 % )                  ;
;     Dedicated logic registers      ; 152 / 33,216 ( < 1 % )                  ;
; Total registers                    ; 152                                     ;
; Total pins                         ; 37 / 475 ( 8 % )                        ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 512 / 483,840 ( < 1 % )                 ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                          ;
; Total PLLs                         ; 0 / 4 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C35F672C6                   ;                                ;
; Maximum processors allowed for parallel compilation                ; 1                              ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;