part6.eda.rpt

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EDA Netlist Writer report for part6
Fri May 15 12:02:04 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. Timing Analysis Settings
  6. Timing Analysis Generated Files
  7. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; EDA Netlist Writer Summary                                             ;
+--------------------------------+---------------------------------------+
; EDA Netlist Writer Status      ; Successful - Fri May 15 12:02:04 2009 ;
; Revision Name                  ; part6                                 ;
; Top-level Entity Name          ; part6                                 ;
; Family                         ; Cyclone II                            ;
; Simulation Files Creation      ; Successful                            ;
; Timing Analysis Files Creation ; Successful                            ;
+--------------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                             ;
+--------------------------------------------------------------------------------------------+--------------------+
; Option                                                                                     ; Setting            ;
+--------------------------------------------------------------------------------------------+--------------------+
; Tool Name                                                                                  ; ModelSim (Verilog) ;
; Generate netlist for functional simulation only                                            ; Off                ;
; Time scale                                                                                 ; 1 ps               ;
; Truncate long hierarchy paths                                                              ; Off                ;
; Map illegal HDL characters                                                                 ; Off                ;
; Flatten buses into individual nodes                                                        ; Off                ;
; Maintain hierarchy                                                                         ; Off                ;
; Bring out device-wide set/reset signals as ports                                           ; Off                ;
; Enable glitch filtering                                                                    ; Off                ;
; Do not write top level VHDL entity                                                         ; Off                ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                ;
; Architecture name in VHDL output netlist                                                   ; structure          ;
+--------------------------------------------------------------------------------------------+--------------------+


+--------------------------------------------------------------------+
; Simulation Generated Files                                         ;
+--------------------------------------------------------------------+
; Generated Files                                                    ;
+--------------------------------------------------------------------+
; C:/Users/Sophy/Desktop/LAB_8/part6/simulation/modelsim/part6.vo    ;
; C:/Users/Sophy/Desktop/LAB_8/part6/simulation/modelsim/part6_v.sdo ;
+--------------------------------------------------------------------+


+-----------------------------------------------------------+
; Timing Analysis Settings                                  ;
+-------------------------------------+---------------------+
; Option                              ; Setting             ;
+-------------------------------------+---------------------+
; Tool Name                           ; PrimeTime (Verilog) ;
; Time scale                          ; 1 ps                ;
; Truncate long hierarchy paths       ; Off                 ;
; Map illegal HDL characters          ; Off                 ;
; Flatten buses into individual nodes ; Off                 ;
+-------------------------------------+---------------------+


+--------------------------------------------------------------------+
; Timing Analysis Generated Files                                    ;
+--------------------------------------------------------------------+
; Generated Files                                                    ;
+--------------------------------------------------------------------+
; C:/Users/Sophy/Desktop/LAB_8/part6/timing/primetime/part6.vo       ;
; C:/Users/Sophy/Desktop/LAB_8/part6/timing/primetime/part6_v.sdo    ;
; C:/Users/Sophy/Desktop/LAB_8/part6/timing/primetime/part6_pt_v.tcl ;
+--------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Fri May 15 12:02:02 2009
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off part6 -c part6
Info: Generated simulation netlist is non-hierarchical because the design has SignalTap partitions and/or termination control logic
Info: Generated files "part6.vo" and "part6_v.sdo" in directory "C:/Users/Sophy/Desktop/LAB_8/part6/simulation/modelsim/" for EDA simulation tool
Info: Generated files "part6.vo" and "part6_v.sdo" in directory "C:/Users/Sophy/Desktop/LAB_8/part6/timing/primetime/" for EDA timing analysis tool
Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
Info: Generated PrimeTime Tcl script file C:/Users/Sophy/Desktop/LAB_8/part6/timing/primetime/part6_pt_v.tcl
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 148 megabytes
    Info: Processing ended: Fri May 15 12:02:05 2009
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02