📄 part6.tan.rpt
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 120.02 MHz ( period = 8.332 ns ) ; count:Cnt|y.00100 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 4.197 ns ;
; N/A ; 125.31 MHz ( period = 7.980 ns ) ; count:Cnt|y.01000 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg5 ; CLK ; CLK ; None ; None ; 3.833 ns ;
; N/A ; 129.00 MHz ( period = 7.752 ns ) ; count:Cnt|y.00010 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg5 ; CLK ; CLK ; None ; None ; 3.617 ns ;
; N/A ; 129.12 MHz ( period = 7.745 ns ) ; count:Cnt|y.10011 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg3 ; CLK ; CLK ; None ; None ; 3.610 ns ;
; N/A ; 129.15 MHz ( period = 7.743 ns ) ; count:Cnt|y.10100 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.597 ns ;
; N/A ; 129.32 MHz ( period = 7.733 ns ) ; count:Cnt|y.00010 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg4 ; CLK ; CLK ; None ; None ; 3.598 ns ;
; N/A ; 129.58 MHz ( period = 7.717 ns ) ; count:Cnt|y.11011 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg3 ; CLK ; CLK ; None ; None ; 3.571 ns ;
; N/A ; 129.67 MHz ( period = 7.712 ns ) ; count:Cnt|y.11001 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.566 ns ;
; N/A ; 129.70 MHz ( period = 7.710 ns ) ; count:Cnt|y.10101 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg4 ; CLK ; CLK ; None ; None ; 3.575 ns ;
; N/A ; 129.85 MHz ( period = 7.701 ns ) ; count:Cnt|y.00100 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg1 ; CLK ; CLK ; None ; None ; 3.566 ns ;
; N/A ; 130.29 MHz ( period = 7.675 ns ) ; count:Cnt|y.10001 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.529 ns ;
; N/A ; 131.39 MHz ( period = 7.611 ns ) ; count:Cnt|y.00011 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg3 ; CLK ; CLK ; None ; None ; 3.476 ns ;
; N/A ; 133.00 MHz ( period = 7.519 ns ) ; count:Cnt|y.01011 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg3 ; CLK ; CLK ; None ; None ; 3.384 ns ;
; N/A ; 133.39 MHz ( period = 7.497 ns ) ; count:Cnt|y.11000 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.350 ns ;
; N/A ; 133.40 MHz ( period = 7.496 ns ) ; count:Cnt|y.00000 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.349 ns ;
; N/A ; 134.44 MHz ( period = 7.438 ns ) ; count:Cnt|y.00001 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.303 ns ;
; N/A ; 134.81 MHz ( period = 7.418 ns ) ; count:Cnt|y.00101 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.283 ns ;
; N/A ; 135.54 MHz ( period = 7.378 ns ) ; count:Cnt|y.10101 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.243 ns ;
; N/A ; 137.08 MHz ( period = 7.295 ns ) ; count:Cnt|y.11100 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK ; CLK ; None ; None ; 3.149 ns ;
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