part6.tan.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                         ;
+---------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                     ; To                                                                                                                                                               ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.656 ns                                       ; Wren                                     ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; --                           ; CLK                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 19.214 ns                                      ; count:Cnt|y.00010                        ; SEG_DATA[3]                                                                                                                                                      ; CLK                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 16.962 ns                                      ; Data[7]                                  ; SEG_DATA[6]                                                                                                                                                      ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.962 ns                                       ; altera_internal_jtag~TDIUTAP             ; sld_hub:sld_hub_inst|tdo_bypass_reg                                                                                                                              ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 120.02 MHz ( period = 8.332 ns )               ; count:Cnt|y.00100                        ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~porta_address_reg2 ; CLK                          ; CLK                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; sld_hub:sld_hub_inst|virtual_ir_scan_reg ; myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ram_block4a0~portb_we_reg       ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                          ;                                                                                                                                                                  ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;