part6_v.sdo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "part6")
  (DATE "05/15/2009 12:02:03")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (6824:6824:6824) (6824:6824:6824))
        (PORT d[1] (6709:6709:6709) (6709:6709:6709))
        (PORT d[2] (6563:6563:6563) (6563:6563:6563))
        (PORT d[3] (6696:6696:6696) (6696:6696:6696))
        (PORT d[4] (6393:6393:6393) (6393:6393:6393))
        (PORT d[5] (6450:6450:6450) (6450:6450:6450))
        (PORT d[6] (6446:6446:6446) (6446:6446:6446))
        (PORT d[7] (6553:6553:6553) (6553:6553:6553))
        (PORT clk (1620:1620:1620) (1620:1620:1620))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (920:920:920) (920:920:920))
        (PORT d[1] (921:921:921) (921:921:921))
        (PORT d[2] (1420:1420:1420) (1420:1420:1420))
        (PORT d[3] (953:953:953) (953:953:953))
        (PORT d[4] (914:914:914) (914:914:914))
        (PORT d[5] (934:934:934) (934:934:934))
        (PORT clk (1621:1621:1621) (1621:1621:1621))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1076:1076:1076) (1076:1076:1076))
        (PORT clk (1621:1621:1621) (1621:1621:1621))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1621:1621:1621) (1621:1621:1621))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1830:1830:1830) (1830:1830:1830))
        (IOPATH (posedge clk) pulse (0:0:0) (1011:1011:1011))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1830:1830:1830) (1830:1830:1830))
        (IOPATH (posedge clk) pulse (0:0:0) (2123:2123:2123))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1830:1830:1830) (1830:1830:1830))
        (IOPATH (posedge clk) pulse (0:0:0) (2993:2993:2993))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1425:1425:1425) (1425:1425:1425))
        (PORT d[1] (1189:1189:1189) (1189:1189:1189))
        (PORT d[2] (1174:1174:1174) (1174:1174:1174))
        (PORT d[3] (1185:1185:1185) (1185:1185:1185))
        (PORT d[4] (1740:1740:1740) (1740:1740:1740))
        (PORT d[5] (1178:1178:1178) (1178:1178:1178))
        (PORT d[6] (1187:1187:1187) (1187:1187:1187))
        (PORT d[7] (1758:1758:1758) (1758:1758:1758))
        (PORT clk (1632:1632:1632) (1632:1632:1632))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (929:929:929) (929:929:929))
        (PORT d[1] (1440:1440:1440) (1440:1440:1440))
        (PORT d[2] (1434:1434:1434) (1434:1434:1434))
        (PORT d[3] (1466:1466:1466) (1466:1466:1466))
        (PORT d[4] (1474:1474:1474) (1474:1474:1474))
        (PORT d[5] (1439:1439:1439) (1439:1439:1439))
        (PORT clk (1648:1648:1648) (1648:1648:1648))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.rewe_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1316:1316:1316) (1316:1316:1316))
        (PORT clk (1648:1648:1648) (1648:1648:1648))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (35:35:35))
      (HOLD d (posedge clk) (234:234:234))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.active_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1648:1648:1648) (1648:1648:1648))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1857:1857:1857))
        (IOPATH (posedge clk) pulse (0:0:0) (1994:1994:1994))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1857:1857:1857))
        (IOPATH (posedge clk) pulse (0:0:0) (2093:2093:2093))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|altsyncram1\|altsyncram3\|ram_block4a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1857:1857:1857) (1857:1857:1857))
        (IOPATH (posedge clk) pulse (0:0:0) (2991:2991:2991))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE Ram\|altsyncram_component\|auto_generated\|mgl_prim2\|ram_rom_data_shift_cntr_reg\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1564:1564:1564) (1564:1564:1564))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1550:1550:1550) (1550:1550:1550))
        (PORT sclr (738:738:738) (738:738:738))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD sclr (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~132)
    (DELAY
      (ABSOLUTE
        (PORT datab (1551:1551:1551) (1551:1551:1551))
        (IOPATH datab combout (420:420:420) (420:420:420))
        (IOPATH datab cout (393:393:393) (393:393:393))
        (IOPATH datad combout (150:150:150) (150:150:150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~134)
    (DELAY
      (ABSOLUTE
        (PORT dataa (507:507:507) (507:507:507))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (414:414:414) (414:414:414))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~136)
    (DELAY
      (ABSOLUTE
        (PORT datab (504:504:504) (504:504:504))
        (IOPATH datab combout (420:420:420) (420:420:420))
        (IOPATH datab cout (393:393:393) (393:393:393))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~138)
    (DELAY
      (ABSOLUTE
        (PORT dataa (518:518:518) (518:518:518))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (414:414:414) (414:414:414))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~140)
    (DELAY
      (ABSOLUTE
        (PORT dataa (518:518:518) (518:518:518))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (414:414:414) (414:414:414))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~142)
    (DELAY
      (ABSOLUTE
        (PORT datab (492:492:492) (492:492:492))
        (IOPATH datab combout (420:420:420) (420:420:420))
        (IOPATH datab cout (393:393:393) (393:393:393))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~144)
    (DELAY
      (ABSOLUTE
        (PORT dataa (508:508:508) (508:508:508))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (504:504:504) (504:504:504))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (159:159:159) (159:159:159))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~146)
    (DELAY
      (ABSOLUTE
        (PORT dataa (770:770:770) (770:770:770))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (414:414:414) (414:414:414))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~148)
    (DELAY
      (ABSOLUTE
        (PORT datab (495:495:495) (495:495:495))
        (IOPATH datab combout (420:420:420) (420:420:420))
        (IOPATH datab cout (393:393:393) (393:393:393))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~150)
    (DELAY
      (ABSOLUTE
        (PORT dataa (469:469:469) (469:469:469))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (414:414:414) (414:414:414))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
        (IOPATH cin cout (71:71:71) (71:71:71))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add1\~152)
    (DELAY
      (ABSOLUTE
        (PORT datad (486:486:486) (486:486:486))
        (IOPATH datad combout (150:150:150) (150:150:150))
        (IOPATH cin combout (410:410:410) (410:410:410))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE Add2\~132)
    (DELAY
      (ABSOLUTE
        (PORT dataa (498:498:498) (498:498:498))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH dataa cout (414:414:414) (414:414:414))