part6.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

wire \sld_hub_inst|irf_reg[1][0]~270_combout ;
wire \sld_hub_inst|irf_reg[1][4]~regout ;
wire \sld_hub_inst|clr_reg~_wirecell_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg~29_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg~regout ;
wire \sld_hub_inst|irsr_reg~522_combout ;
wire \sld_hub_inst|shadow_irf_reg~265_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][0]~266_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][0]~267_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][0]~regout ;
wire \sld_hub_inst|irf_reg~267_combout ;
wire \sld_hub_inst|irf_reg[1][0]~regout ;
wire \sld_hub_inst|irf_reg[1][0]~clkctrl_outclk ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0]~feeder_combout ;
wire \sld_hub_inst|irsr_reg~519_combout ;
wire \sld_hub_inst|hub_mode_reg~465_combout ;
wire \sld_hub_inst|hub_mode_reg[2]~0_combout ;
wire \sld_hub_inst|hub_mode_reg[2]~466_combout ;
wire \sld_hub_inst|clr_reg_proc~0_combout ;
wire \sld_hub_inst|clr_reg~regout ;
wire \sld_hub_inst|clr_reg~clkctrl_outclk ;
wire \sld_hub_inst|shadow_irf_reg~270_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][3]~regout ;
wire \sld_hub_inst|irf_reg~273_combout ;
wire \sld_hub_inst|irf_reg[1][3]~regout ;
wire \sld_hub_inst|irf_reg[1][3]~clkctrl_outclk ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|Equal1~33_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0]~47 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~48_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~49 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~50_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|Equal1~32_combout ;
wire \sld_hub_inst|shadow_irf_reg~269_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][2]~regout ;
wire \sld_hub_inst|irf_reg~272_combout ;
wire \sld_hub_inst|irf_reg[1][2]~regout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~16_combout ;
wire \sld_hub_inst|shadow_irf_reg~268_combout ;
wire \sld_hub_inst|shadow_irf_reg[1][1]~regout ;
wire \sld_hub_inst|irf_reg~271_combout ;
wire \sld_hub_inst|irf_reg[1][1]~regout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~71 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~72_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[1]~feeder_combout ;
wire \sld_hub_inst|irsr_reg~523_combout ;
wire \sld_hub_inst|Equal6~56_combout ;
wire \sld_hub_inst|tdo~424_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|clear_signal~combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0]~215_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[3]~224 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[4]~225_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0]~218_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1718_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[1]~219_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1725_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0]~217_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0]~216 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[1]~220 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[2]~221_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[2]~222 ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[3]~223_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1723_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1726_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1732_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1727_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~15_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]~1722_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1724_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1731_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1721_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|bypass_reg_out~56_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|bypass_reg_out~regout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|tdo~200_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|tdo~201_combout ;
wire \sld_hub_inst|tdo~425_combout ;
wire \sld_hub_inst|tdo~426_combout ;
wire \sld_hub_inst|tdo~regout ;
wire \sld_hub_inst|tdo~_wirecell_combout ;
wire \altera_internal_jtag~TDIUTAP ;
wire \sld_hub_inst|jtag_ir_reg[9]~feeder_combout ;
wire \sld_hub_inst|jtag_ir_reg[8]~feeder_combout ;
wire \sld_hub_inst|jtag_ir_reg[4]~feeder_combout ;
wire \sld_hub_inst|jtag_ir_reg[2]~feeder_combout ;
wire \sld_hub_inst|jtag_ir_reg[0]~feeder_combout ;
wire \sld_hub_inst|Equal1~29_combout ;
wire \sld_hub_inst|virtual_ir_scan_reg~regout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|enable_write~9_combout ;
wire \CLK~combout ;
wire \CLK~clkctrl_outclk ;
wire \altera_internal_jtag~TCKUTAP ;
wire \altera_internal_jtag~TCKUTAPclkctrl_outclk ;
wire \~GND~combout ;
wire \Address_in[0]~220_combout ;
wire \Address_in[1]~221_combout ;
wire \Cnt|WideOr2~39_combout ;
wire \Cnt|WideOr2~40_combout ;
wire \Address_in[2]~222_combout ;
wire \Add1~133 ;
wire \Add1~135 ;
wire \Add1~136_combout ;
wire \Clock1~regout ;
wire \Address_in[3]~223_combout ;
wire \Cnt|WideOr0~55_combout ;
wire \Cnt|WideOr0~56_combout ;
wire \Cnt|WideOr0~57_combout ;
wire \Address_in[4]~224_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|process_0~2_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~742_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|process_0~4_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0]~740_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~741_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~744_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~743_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~746_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~745_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~747_combout ;
wire \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~739_combout ;
wire \D2|out[0]~445_combout ;
wire \SEG_DATA~3457_combout ;
wire \SEG_DATA~3458_combout ;
wire \D1|out[0]~1071_combout ;
wire \SEG_DATA~3494_combout ;
wire \SEG_DATA~3459_combout ;
wire \SEG_DATA~3463_combout ;
wire \SEG_DATA~3499_combout ;
wire \SEG_DATA~3500_combout ;
wire \SEG_DATA~3501_combout ;
wire \SEG_DATA~3460_combout ;
wire \SEG_DATA~3461_combout ;
wire \SEG_DATA~3502_combout ;
wire \SEG_DATA~3465_combout ;
wire \SEG_DATA~3467_combout ;
wire \SEG_DATA~3469_combout ;
wire \D2|out[2]~446_combout ;
wire \D4|out[2]~523_combout ;
wire \SEG_DATA~3466_combout ;
wire \D5|out[2]~812_combout ;
wire \SEG_DATA~3470_combout ;
wire \D3|out[3]~445_combout ;
wire \D5|out[3]~813_combout ;
wire \SEG_DATA~3471_combout ;
wire \D2|out[3]~447_combout ;
wire \SEG_DATA~3472_combout ;
wire \D1|out[3]~1073_combout ;
wire \SEG_DATA~3495_combout ;
wire \SEG_DATA~3473_combout ;
wire \SEG_DATA~3477_combout ;
wire \SEG_DATA~3476_combout ;
wire \SEG_DATA~3478_combout ;
wire \D1|out[4]~1074_combout ;
wire \SEG_DATA~3479_combout ;
wire \SEG_DATA~3475_combout ;
wire \SEG_DATA~3497_combout ;
wire \SEG_DATA~3498_combout ;
wire \SEG_DATA~3486_combout ;
wire \SEG_DATA~3496_combout ;
wire \SEG_DATA~3481_combout ;
wire \SEG_DATA~3483_combout ;
wire \SEG_DATA~3484_combout ;
wire \SEG_DATA~3485_combout ;
wire \SEG_DATA~3487_combout ;
wire \D5|out[6]~814_combout ;
wire \SEG_DATA~3489_combout ;
wire \SEG_DATA~3488_combout ;
wire \SEG_DATA~3490_combout ;
wire \SEG_DATA~3492_combout ;
wire \SEG_DATA~3493_combout ;
wire \altera_reserved_tms~combout ;
wire \altera_internal_jtag~TDO ;
wire [4:0] \Address~combout ;
wire [7:0] \Data~combout ;
wire [2:0] cnt;
wire [10:0] temp1;
wire [10:0] temp2;
wire [3:0] \sld_hub_inst|hub_info_reg|WORD_SR ;
wire [4:0] \sld_hub_inst|hub_info_reg|word_counter ;
wire [15:0] \sld_hub_inst|shadow_jsm|state ;
wire [2:0] \sld_hub_inst|shadow_jsm|tms_cnt ;
wire [2:0] \sld_hub_inst|hub_mode_reg ;
wire [5:0] \sld_hub_inst|irsr_reg ;
wire [9:0] \sld_hub_inst|jtag_ir_reg ;
wire [3:0] \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR ;
wire [4:0] \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|word_counter ;
wire [3:0] \Ram|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg ;
wire [4:0] \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg ;
wire [7:0] \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg ;
wire [3:0] \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg ;
wire [7:0] \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a ;
wire [7:0] \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b ;

wire [7:0] \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus ;
wire [7:0] \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus ;

assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [0] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [0];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [1] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [1];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [2] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [2];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [3] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [3];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [4] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [4];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [5] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [5];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [6] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [6];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_a [7] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus [7];

assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [0] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [0];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [1] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [1];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [2] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [2];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [3] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [3];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [4] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [4];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [5] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [5];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [6] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [6];
assign \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|q_b [7] = \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus [7];

// atom is at M4K_X52_Y20
cycloneii_ram_block \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 (
	.portawe(\WrenC~combout ),
	.portaaddrstall(gnd),
	.portbrewe(\Ram|altsyncram_component|auto_generated|mgl_prim2|enable_write~9_combout ),
	.portbaddrstall(gnd),
	.clk0(\CLK~clkctrl_outclk ),
	.clk1(\altera_internal_jtag~TCKUTAPclkctrl_outclk ),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\Data~combout [7],\Data~combout [6],\Data~combout [5],\Data~combout [4],\Data~combout [3],\Data~combout [2],\Data~combout [1],\Data~combout [0]}),
	.portaaddr({\Address_in[4]~224_combout ,\Address_in[3]~223_combout ,\Address_in[2]~222_combout ,\Address_in[1]~221_combout ,\Address_in[0]~220_combout ,\~GND~combout }),
	.portabyteenamasks(1'b1),
	.portbdatain({\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [7],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [6],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [5],
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [4],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [3],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [2],
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [1],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg [0]}),
	.portbaddr({\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg [4],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg [3],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg [2],
\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg [1],\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg [0],\~GND~combout }),
	.portbbyteenamasks(1'b1),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTADATAOUT_bus ),
	.portbdataout(\Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0_PORTBDATAOUT_bus ));
// synopsys translate_off
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .data_interleave_offset_in_bits = 1;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .data_interleave_width_in_bits = 1;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .init_file = "myram.mif";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .init_file_layout = "port_a";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .logical_ram_name = "myram:Ram|altsyncram:altsyncram_component|altsyncram_bvj1:auto_generated|altsyncram_jbf2:altsyncram1|altsyncram_p592:altsyncram3|ALTSYNCRAM";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .mixed_port_feed_through_mode = "dont_care";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .operation_mode = "bidir_dual_port";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_address_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_address_width = 6;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_byte_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_byte_enable_clock = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_in_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_out_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_out_clock = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_data_width = 8;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_first_address = 0;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_first_bit_number = 0;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_last_address = 63;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_logical_ram_depth = 64;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_logical_ram_width = 8;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_a_write_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_address_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_address_clock = "clock1";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_address_width = 6;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_byte_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_in_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_in_clock = "clock1";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_out_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_out_clock = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_data_width = 8;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_first_address = 0;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_first_bit_number = 0;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_last_address = 63;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_logical_ram_depth = 64;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_logical_ram_width = 8;
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_read_enable_write_enable_clear = "none";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .port_b_read_enable_write_enable_clock = "clock1";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .ram_block_type = "M4K";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .safe_write = "err_on_2clk";
defparam \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 .mem_init0 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000;
// synopsys translate_on

// atom is at LCFF_X45_Y20_N7
cycloneii_lcell_ff \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3] (
	.clk(\altera_internal_jtag~TCKUTAPclkctrl_outclk ),
	.datain(\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~52_combout ),
	.sdata(gnd),
	.aclr(\sld_hub_inst|irf_reg[1][3]~clkctrl_outclk ),
	.sclr(\Ram|altsyncram_component|auto_generated|mgl_prim2|Equal1~33_combout ),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg [3]));

// atom is at LCCOMB_X50_Y18_N2
cycloneii_lcell_comb \Add1~132 (
// Equation(s):
// \Add1~132_combout  = cnt[0] $ VCC
// \Add1~133  = CARRY(cnt[0])

	.dataa(vcc),
	.datab(cnt[0]),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\Add1~132_combout ),
	.cout(\Add1~133 ));
// synopsys translate_off
defparam \Add1~132 .lut_mask = 16'h33CC;
defparam \Add1~132 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X50_Y18_N4
cycloneii_lcell_comb \Add1~134 (
// Equation(s):
// \Add1~134_combout  = temp1[1] & !\Add1~133  # !temp1[1] & (\Add1~133  # GND)
// \Add1~135  = CARRY(!\Add1~133  # !temp1[1])

	.dataa(temp1[1]),