part6_modelsim.xrf

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

instance = comp, \sld_hub_inst|tdo~_wirecell , sld_hub_inst|tdo~_wirecell, part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[9]~feeder , sld_hub_inst|jtag_ir_reg[9]~feeder, part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[9] , sld_hub_inst|jtag_ir_reg[9], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[8]~feeder , sld_hub_inst|jtag_ir_reg[8]~feeder, part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[8] , sld_hub_inst|jtag_ir_reg[8], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[7] , sld_hub_inst|jtag_ir_reg[7], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[6] , sld_hub_inst|jtag_ir_reg[6], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[5] , sld_hub_inst|jtag_ir_reg[5], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[4]~feeder , sld_hub_inst|jtag_ir_reg[4]~feeder, part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[4] , sld_hub_inst|jtag_ir_reg[4], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[3] , sld_hub_inst|jtag_ir_reg[3], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[2]~feeder , sld_hub_inst|jtag_ir_reg[2]~feeder, part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[2] , sld_hub_inst|jtag_ir_reg[2], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[1] , sld_hub_inst|jtag_ir_reg[1], part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[0]~feeder , sld_hub_inst|jtag_ir_reg[0]~feeder, part6, 1
instance = comp, \sld_hub_inst|jtag_ir_reg[0] , sld_hub_inst|jtag_ir_reg[0], part6, 1
instance = comp, \sld_hub_inst|Equal1~29 , sld_hub_inst|Equal1~29, part6, 1
instance = comp, \sld_hub_inst|virtual_ir_scan_reg , sld_hub_inst|virtual_ir_scan_reg, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|enable_write~9 , Ram|altsyncram_component|auto_generated|mgl_prim2|enable_write~9, part6, 1
instance = comp, \CLK~I , CLK, part6, 1
instance = comp, \CLK~clkctrl , CLK~clkctrl, part6, 1
instance = comp, \altera_internal_jtag~TCKUTAPclkctrl , altera_internal_jtag~TCKUTAPclkctrl, part6, 1
instance = comp, \Data[0]~I , Data[0], part6, 1
instance = comp, \~GND , ~GND, part6, 1
instance = comp, \Address[0]~I , Address[0], part6, 1
instance = comp, \Address_in[0]~220 , Address_in[0]~220, part6, 1
instance = comp, \Address[1]~I , Address[1], part6, 1
instance = comp, \Address_in[1]~221 , Address_in[1]~221, part6, 1
instance = comp, \Address[2]~I , Address[2], part6, 1
instance = comp, \Cnt|WideOr2~39 , Cnt|WideOr2~39, part6, 1
instance = comp, \Cnt|WideOr2~40 , Cnt|WideOr2~40, part6, 1
instance = comp, \Address_in[2]~222 , Address_in[2]~222, part6, 1
instance = comp, \Address[3]~I , Address[3], part6, 1
instance = comp, \Address_in[3]~223 , Address_in[3]~223, part6, 1
instance = comp, \Address[4]~I , Address[4], part6, 1
instance = comp, \Cnt|WideOr0~55 , Cnt|WideOr0~55, part6, 1
instance = comp, \Cnt|WideOr0~56 , Cnt|WideOr0~56, part6, 1
instance = comp, \Cnt|WideOr0~57 , Cnt|WideOr0~57, part6, 1
instance = comp, \Address_in[4]~224 , Address_in[4]~224, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|process_0~2 , Ram|altsyncram_component|auto_generated|mgl_prim2|process_0~2, part6, 1
instance = comp, \Data[4]~I , Data[4], part6, 1
instance = comp, \Data[5]~I , Data[5], part6, 1
instance = comp, \Data[6]~I , Data[6], part6, 1
instance = comp, \Data[7]~I , Data[7], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~742 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~742, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|process_0~4 , Ram|altsyncram_component|auto_generated|mgl_prim2|process_0~4, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0]~740 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0]~740, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~741 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~741, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~744 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~744, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~743 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~743, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[4] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[4], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~746 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~746, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[3] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[3], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~745 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~745, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[2] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[2], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~747 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~747, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[1] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[1], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~739 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~739, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0], part6, 1
instance = comp, \D2|out[0]~445 , D2|out[0]~445, part6, 1
instance = comp, \SEG_DATA~3457 , SEG_DATA~3457, part6, 1
instance = comp, \SEG_DATA~3458 , SEG_DATA~3458, part6, 1
instance = comp, \D1|out[0]~1071 , D1|out[0]~1071, part6, 1
instance = comp, \SEG_DATA~3494 , SEG_DATA~3494, part6, 1
instance = comp, \SEG_DATA~3459 , SEG_DATA~3459, part6, 1
instance = comp, \SEG_DATA~3463 , SEG_DATA~3463, part6, 1
instance = comp, \SEG_DATA~3499 , SEG_DATA~3499, part6, 1
instance = comp, \SEG_DATA~3500 , SEG_DATA~3500, part6, 1
instance = comp, \SEG_DATA~3501 , SEG_DATA~3501, part6, 1
instance = comp, \SEG_DATA~3460 , SEG_DATA~3460, part6, 1
instance = comp, \SEG_DATA~3461 , SEG_DATA~3461, part6, 1
instance = comp, \SEG_DATA~3502 , SEG_DATA~3502, part6, 1
instance = comp, \SEG_DATA~3465 , SEG_DATA~3465, part6, 1
instance = comp, \SEG_DATA~3467 , SEG_DATA~3467, part6, 1
instance = comp, \SEG_DATA~3469 , SEG_DATA~3469, part6, 1
instance = comp, \D2|out[2]~446 , D2|out[2]~446, part6, 1
instance = comp, \D4|out[2]~523 , D4|out[2]~523, part6, 1
instance = comp, \SEG_DATA~3466 , SEG_DATA~3466, part6, 1
instance = comp, \D5|out[2]~812 , D5|out[2]~812, part6, 1
instance = comp, \SEG_DATA~3470 , SEG_DATA~3470, part6, 1
instance = comp, \D3|out[3]~445 , D3|out[3]~445, part6, 1
instance = comp, \D5|out[3]~813 , D5|out[3]~813, part6, 1
instance = comp, \SEG_DATA~3471 , SEG_DATA~3471, part6, 1
instance = comp, \D2|out[3]~447 , D2|out[3]~447, part6, 1
instance = comp, \SEG_DATA~3472 , SEG_DATA~3472, part6, 1
instance = comp, \D1|out[3]~1073 , D1|out[3]~1073, part6, 1
instance = comp, \SEG_DATA~3495 , SEG_DATA~3495, part6, 1
instance = comp, \SEG_DATA~3473 , SEG_DATA~3473, part6, 1
instance = comp, \SEG_DATA~3477 , SEG_DATA~3477, part6, 1
instance = comp, \SEG_DATA~3476 , SEG_DATA~3476, part6, 1
instance = comp, \SEG_DATA~3478 , SEG_DATA~3478, part6, 1
instance = comp, \D1|out[4]~1074 , D1|out[4]~1074, part6, 1
instance = comp, \SEG_DATA~3479 , SEG_DATA~3479, part6, 1
instance = comp, \SEG_DATA~3475 , SEG_DATA~3475, part6, 1
instance = comp, \SEG_DATA~3497 , SEG_DATA~3497, part6, 1
instance = comp, \SEG_DATA~3498 , SEG_DATA~3498, part6, 1
instance = comp, \SEG_DATA~3486 , SEG_DATA~3486, part6, 1
instance = comp, \SEG_DATA~3496 , SEG_DATA~3496, part6, 1
instance = comp, \SEG_DATA~3481 , SEG_DATA~3481, part6, 1
instance = comp, \SEG_DATA~3483 , SEG_DATA~3483, part6, 1
instance = comp, \SEG_DATA~3484 , SEG_DATA~3484, part6, 1
instance = comp, \SEG_DATA~3485 , SEG_DATA~3485, part6, 1
instance = comp, \SEG_DATA~3487 , SEG_DATA~3487, part6, 1
instance = comp, \D5|out[6]~814 , D5|out[6]~814, part6, 1
instance = comp, \SEG_DATA~3489 , SEG_DATA~3489, part6, 1
instance = comp, \SEG_DATA~3488 , SEG_DATA~3488, part6, 1
instance = comp, \SEG_DATA~3490 , SEG_DATA~3490, part6, 1
instance = comp, \SEG_DATA~3492 , SEG_DATA~3492, part6, 1
instance = comp, \SEG_DATA~3493 , SEG_DATA~3493, part6, 1
instance = comp, \altera_reserved_tms~I , altera_reserved_tms, part6, 1
instance = comp, \sld_hub_inst|shadow_jsm|state[0]~_wirecell , sld_hub_inst|shadow_jsm|state[0]~_wirecell, part6, 1
instance = comp, \LED~I , LED, part6, 1
instance = comp, \SEG_COM[0]~I , SEG_COM[0], part6, 1
instance = comp, \SEG_COM[1]~I , SEG_COM[1], part6, 1
instance = comp, \SEG_COM[2]~I , SEG_COM[2], part6, 1
instance = comp, \SEG_COM[3]~I , SEG_COM[3], part6, 1
instance = comp, \SEG_COM[4]~I , SEG_COM[4], part6, 1
instance = comp, \SEG_COM[5]~I , SEG_COM[5], part6, 1
instance = comp, \SEG_COM[6]~I , SEG_COM[6], part6, 1
instance = comp, \SEG_COM[7]~I , SEG_COM[7], part6, 1
instance = comp, \SEG_DATA[0]~I , SEG_DATA[0], part6, 1
instance = comp, \SEG_DATA[1]~I , SEG_DATA[1], part6, 1
instance = comp, \SEG_DATA[2]~I , SEG_DATA[2], part6, 1
instance = comp, \SEG_DATA[3]~I , SEG_DATA[3], part6, 1
instance = comp, \SEG_DATA[4]~I , SEG_DATA[4], part6, 1
instance = comp, \SEG_DATA[5]~I , SEG_DATA[5], part6, 1
instance = comp, \SEG_DATA[6]~I , SEG_DATA[6], part6, 1
instance = comp, \SEG_DATA[7]~I , SEG_DATA[7], part6, 1
instance = comp, \altera_reserved_tdo~I , altera_reserved_tdo, part6, 1