part6_modelsim.xrf

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

vendor_name = ModelSim
source_file = 1, part6
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/part6.v
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/part6.vwf
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/part6.hex
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/myram.mif
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/db/part6.cbx.xml
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/aglobal81.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/altrom.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/altram.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/altqpram.inc
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/cbx.lst
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_bvj1.tdf
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_jbf2.tdf
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part6/db/altsyncram_p592.tdf
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/sld_rom_sr.vhd
source_file = 1, c:/altera/81/quartus/libraries/megafunctions/sld_hub.vhd
design_name = part6
instance = comp, \Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0 , Ram|altsyncram_component|auto_generated|altsyncram1|altsyncram3|ram_block4a0, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3] , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3], part6, 1
instance = comp, \Add1~132 , Add1~132, part6, 1
instance = comp, \Add1~134 , Add1~134, part6, 1
instance = comp, \Add1~136 , Add1~136, part6, 1
instance = comp, \Add1~138 , Add1~138, part6, 1
instance = comp, \Add1~140 , Add1~140, part6, 1
instance = comp, \Add1~142 , Add1~142, part6, 1
instance = comp, \Add1~144 , Add1~144, part6, 1
instance = comp, \Add1~146 , Add1~146, part6, 1
instance = comp, \Add1~148 , Add1~148, part6, 1
instance = comp, \Add1~150 , Add1~150, part6, 1
instance = comp, \Add1~152 , Add1~152, part6, 1
instance = comp, \Add2~132 , Add2~132, part6, 1
instance = comp, \Add2~134 , Add2~134, part6, 1
instance = comp, \Add2~136 , Add2~136, part6, 1
instance = comp, \Add2~138 , Add2~138, part6, 1
instance = comp, \Add2~140 , Add2~140, part6, 1
instance = comp, \Add2~142 , Add2~142, part6, 1
instance = comp, \Add2~144 , Add2~144, part6, 1
instance = comp, \Add2~146 , Add2~146, part6, 1
instance = comp, \Add2~148 , Add2~148, part6, 1
instance = comp, \Add2~150 , Add2~150, part6, 1
instance = comp, \Add2~152 , Add2~152, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~50 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~50, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~52 , Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~52, part6, 1
instance = comp, \Cnt|WideOr3~97 , Cnt|WideOr3~97, part6, 1
instance = comp, \Cnt|WideOr1~98 , Cnt|WideOr1~98, part6, 1
instance = comp, \D4|out[0]~522 , D4|out[0]~522, part6, 1
instance = comp, \SEG_DATA~3462 , SEG_DATA~3462, part6, 1
instance = comp, \SEG_DATA~3464 , SEG_DATA~3464, part6, 1
instance = comp, \D3|out[2]~444 , D3|out[2]~444, part6, 1
instance = comp, \D1|out[2]~1072 , D1|out[2]~1072, part6, 1
instance = comp, \SEG_DATA~3468 , SEG_DATA~3468, part6, 1
instance = comp, \D4|out[3]~524 , D4|out[3]~524, part6, 1
instance = comp, \SEG_DATA~3474 , SEG_DATA~3474, part6, 1
instance = comp, \SEG_DATA~3480 , SEG_DATA~3480, part6, 1
instance = comp, \SEG_DATA~3482 , SEG_DATA~3482, part6, 1
instance = comp, \D4|out[6]~525 , D4|out[6]~525, part6, 1
instance = comp, \D1|out[6]~1075 , D1|out[6]~1075, part6, 1
instance = comp, \SEG_DATA~3491 , SEG_DATA~3491, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1717 , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1717, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1719 , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1719, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1720 , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1720, part6, 1
instance = comp, \temp1[7] , temp1[7], part6, 1
instance = comp, \temp1[6] , temp1[6], part6, 1
instance = comp, \temp1[5] , temp1[5], part6, 1
instance = comp, \temp1[4] , temp1[4], part6, 1
instance = comp, \temp1[3] , temp1[3], part6, 1
instance = comp, \temp1[1] , temp1[1], part6, 1
instance = comp, \temp1[8] , temp1[8], part6, 1
instance = comp, \temp1[9] , temp1[9], part6, 1
instance = comp, \Equal0~140 , Equal0~140, part6, 1
instance = comp, \temp1[10] , temp1[10], part6, 1
instance = comp, \Equal0~141 , Equal0~141, part6, 1
instance = comp, \Equal0~142 , Equal0~142, part6, 1
instance = comp, \Equal0~143 , Equal0~143, part6, 1
instance = comp, \temp2[5] , temp2[5], part6, 1
instance = comp, \temp2[4] , temp2[4], part6, 1
instance = comp, \temp2[3] , temp2[3], part6, 1
instance = comp, \temp2[2] , temp2[2], part6, 1
instance = comp, \temp2[1] , temp2[1], part6, 1
instance = comp, \temp2[0] , temp2[0], part6, 1
instance = comp, \temp2[6] , temp2[6], part6, 1
instance = comp, \temp2[8] , temp2[8], part6, 1
instance = comp, \temp2[7] , temp2[7], part6, 1
instance = comp, \temp2[9] , temp2[9], part6, 1
instance = comp, \Equal1~140 , Equal1~140, part6, 1
instance = comp, \temp2[10] , temp2[10], part6, 1
instance = comp, \Equal1~141 , Equal1~141, part6, 1
instance = comp, \Equal1~142 , Equal1~142, part6, 1
instance = comp, \Clock~18 , Clock~18, part6, 1
instance = comp, \temp1~283 , temp1~283, part6, 1
instance = comp, \temp1~284 , temp1~284, part6, 1
instance = comp, \temp1~285 , temp1~285, part6, 1
instance = comp, \temp1~286 , temp1~286, part6, 1
instance = comp, \temp1~287 , temp1~287, part6, 1
instance = comp, \temp1~288 , temp1~288, part6, 1
instance = comp, \temp2~316 , temp2~316, part6, 1
instance = comp, \temp2~317 , temp2~317, part6, 1
instance = comp, \temp2~318 , temp2~318, part6, 1
instance = comp, \temp2~319 , temp2~319, part6, 1
instance = comp, \temp2~320 , temp2~320, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3] , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3], part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1728 , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1728, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1729 , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1729, part6, 1
instance = comp, \Ram|altsyncram_component|auto_generated|mgl_prim2|ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1730 , Ram|altsyncram_component|auto_generated|mgl_prim2|\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR~1730, part6, 1
instance = comp, \D1|out[1]~1070 , D1|out[1]~1070, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[0] , sld_hub_inst|hub_info_reg|word_counter[0], part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[2] , sld_hub_inst|hub_info_reg|word_counter[2], part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[3] , sld_hub_inst|hub_info_reg|word_counter[3], part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[4] , sld_hub_inst|hub_info_reg|word_counter[4], part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[1] , sld_hub_inst|hub_info_reg|word_counter[1], part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[0]~246 , sld_hub_inst|hub_info_reg|word_counter[0]~246, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[1]~250 , sld_hub_inst|hub_info_reg|word_counter[1]~250, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[2]~252 , sld_hub_inst|hub_info_reg|word_counter[2]~252, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[3]~254 , sld_hub_inst|hub_info_reg|word_counter[3]~254, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|word_counter[4]~256 , sld_hub_inst|hub_info_reg|word_counter[4]~256, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|WORD_SR[0] , sld_hub_inst|hub_info_reg|WORD_SR[0], part6, 1
instance = comp, \sld_hub_inst|irsr_reg[3]~517 , sld_hub_inst|irsr_reg[3]~517, part6, 1
instance = comp, \sld_hub_inst|shadow_irf_reg[1][4] , sld_hub_inst|shadow_irf_reg[1][4], part6, 1
instance = comp, \sld_hub_inst|node_ena~685 , sld_hub_inst|node_ena~685, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|clear_signal , sld_hub_inst|hub_info_reg|clear_signal, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|WORD_SR~840 , sld_hub_inst|hub_info_reg|WORD_SR~840, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|WORD_SR[1] , sld_hub_inst|hub_info_reg|WORD_SR[1], part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|WORD_SR~841 , sld_hub_inst|hub_info_reg|WORD_SR~841, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|WORD_SR~842 , sld_hub_inst|hub_info_reg|WORD_SR~842, part6, 1
instance = comp, \sld_hub_inst|irsr_reg[3]~525 , sld_hub_inst|irsr_reg[3]~525, part6, 1
instance = comp, \sld_hub_inst|shadow_irf_reg~271 , sld_hub_inst|shadow_irf_reg~271, part6, 1
instance = comp, \sld_hub_inst|hub_info_reg|WORD_SR~843 , sld_hub_inst|hub_info_reg|WORD_SR~843, part6, 1