part4.fit.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

Fitter report for part4
Fri May 22 09:34:34 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Incremental Compilation Preservation Summary
  5. Incremental Compilation Partition Settings
  6. Incremental Compilation Placement Preservation
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. Bidir Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. Fitter Device Options
 28. Operating Settings and Conditions
 29. Estimated Delay Added for Hold Timing
 30. Advanced Data - General
 31. Advanced Data - Placement Preparation
 32. Advanced Data - Placement
 33. Advanced Data - Routing
 34. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Fri May 22 09:34:34 2009   ;
; Quartus II Version                 ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name                      ; part4                                   ;
; Top-level Entity Name              ; part4                                   ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C35F672C6                            ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 52 / 33,216 ( < 1 % )                   ;
;     Total combinational functions  ; 52 / 33,216 ( < 1 % )                   ;
;     Dedicated logic registers      ; 2 / 33,216 ( < 1 % )                    ;
; Total registers                    ; 2                                       ;
; Total pins                         ; 72 / 475 ( 15 % )                       ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                          ;
; Total PLLs                         ; 0 / 4 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C35F672C6                   ;                                ;
; Maximum processors allowed for parallel compilation                ; 1                              ;                                ;