part4.qsf

来自「This codes is one of my univ projects I 」· QSF 代码 · 共 122 行

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		part4_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY part4
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:10:44  MAY 28, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro"
set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_timing_analysis
set_global_assignment -name SOURCE_FILE part4
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_location_assignment PIN_Y13 -to Address[0]
set_location_assignment PIN_AB12 -to Address[1]
set_location_assignment PIN_AA12 -to Address[2]
set_location_assignment PIN_AD12 -to Address[3]
set_location_assignment PIN_AC12 -to Address[4]
set_location_assignment PIN_U12 -to Address[5]
set_location_assignment PIN_AE11 -to Address[6]
set_location_assignment PIN_Y12 -to Address[7]
set_location_assignment PIN_N1 -to CLK
set_global_assignment -name VECTOR_WAVEFORM_FILE part4.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_location_assignment PIN_W12 -to Data[0]
set_location_assignment PIN_AA11 -to Data[1]
set_location_assignment PIN_Y11 -to Data[2]
set_location_assignment PIN_AD11 -to Data[3]
set_location_assignment PIN_AC11 -to Data[4]
set_location_assignment PIN_AF10 -to Data[5]
set_location_assignment PIN_AE10 -to Data[6]
set_location_assignment PIN_W11 -to Data[7]
set_location_assignment PIN_Y10 -to Write
set_location_assignment PIN_AF7 -to LED
set_location_assignment PIN_E10 -to nCS
set_location_assignment PIN_F10 -to nWE
set_location_assignment PIN_G10 -to nOE
set_location_assignment PIN_Y1 -to SEG_COM[0]
set_location_assignment PIN_Y4 -to SEG_COM[1]
set_location_assignment PIN_Y3 -to SEG_COM[2]
set_location_assignment PIN_W1 -to SEG_COM[3]
set_location_assignment PIN_Y5 -to SEG_COM[4]
set_location_assignment PIN_W3 -to SEG_COM[5]
set_location_assignment PIN_W2 -to SEG_COM[6]
set_location_assignment PIN_V1 -to SEG_COM[7]
set_location_assignment PIN_AF5 -to SEG_DATA[0]
set_location_assignment PIN_AE5 -to SEG_DATA[1]
set_location_assignment PIN_AD6 -to SEG_DATA[2]
set_location_assignment PIN_AC6 -to SEG_DATA[3]
set_location_assignment PIN_AA2 -to SEG_DATA[4]
set_location_assignment PIN_AA1 -to SEG_DATA[5]
set_location_assignment PIN_AA6 -to SEG_DATA[6]
set_location_assignment PIN_AA5 -to SEG_DATA[7]
set_location_assignment PIN_E1 -to SRAM_add[0]
set_location_assignment PIN_F7 -to SRAM_add[1]
set_location_assignment PIN_E5 -to SRAM_add[2]
set_location_assignment PIN_E2 -to SRAM_add[3]
set_location_assignment PIN_D2 -to SRAM_add[4]
set_location_assignment PIN_D1 -to SRAM_add[5]
set_location_assignment PIN_C3 -to SRAM_add[6]
set_location_assignment PIN_C2 -to SRAM_add[7]
set_location_assignment PIN_B5 -to SRAM_add[8]
set_location_assignment PIN_A5 -to SRAM_add[9]
set_location_assignment PIN_D6 -to SRAM_add[10]
set_location_assignment PIN_C6 -to SRAM_add[11]
set_location_assignment PIN_B6 -to SRAM_add[12]
set_location_assignment PIN_A6 -to SRAM_add[13]
set_location_assignment PIN_D7 -to SRAM_add[14]
set_location_assignment PIN_C7 -to SRAM_add[15]
set_location_assignment PIN_B7 -to SRAM_add[16]
set_location_assignment PIN_A7 -to SRAM_add[17]
set_location_assignment PIN_H8 -to SRAM_data[0]
set_location_assignment PIN_E8 -to SRAM_data[1]
set_location_assignment PIN_D8 -to SRAM_data[2]
set_location_assignment PIN_C8 -to SRAM_data[3]
set_location_assignment PIN_B8 -to SRAM_data[4]
set_location_assignment PIN_A8 -to SRAM_data[5]
set_location_assignment PIN_K9 -to SRAM_data[6]
set_location_assignment PIN_J9 -to SRAM_data[7]
set_location_assignment PIN_G9 -to SRAM_data[8]
set_location_assignment PIN_F9 -to SRAM_data[9]
set_location_assignment PIN_D9 -to SRAM_data[10]
set_location_assignment PIN_C9 -to SRAM_data[11]
set_location_assignment PIN_B9 -to SRAM_data[12]
set_location_assignment PIN_A9 -to SRAM_data[13]
set_location_assignment PIN_J10 -to SRAM_data[14]
set_location_assignment PIN_H10 -to SRAM_data[15]
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE part4.vwf
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name MISC_FILE "C:/Users/Sophy/Desktop/Sophy Uni/叼瘤判 角氰/LAB_8/part4/part4.dpf"
set_global_assignment -name MISC_FILE "C:/Users/Sophy/Desktop/LAB_8/part4/part4.dpf"