part4.map.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 22 09:33:52 2009 " "Info: Processing started: Fri May 22 09:33:52 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "part4.v(22) " "Warning (10273): Verilog HDL warning at part4.v(22): extended using \"x\" or \"z\"" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 22 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "part4.v(32) " "Warning (10268): Verilog HDL information at part4.v(32): always construct contains both blocking and non-blocking assignments" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 32 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "part4.v 2 2 " "Warning: Using design file part4.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 part4 " "Info: Found entity 1: part4" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 display " "Info: Found entity 2: display" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 59 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "part4 " "Info: Elaborating entity \"part4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "17 16 part4.v(20) " "Warning (10230): Verilog HDL assignment warning at part4.v(20): truncated value with size 17 to match size of target (16)" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 part4.v(29) " "Warning (10230): Verilog HDL assignment warning at part4.v(29): truncated value with size 32 to match size of target (2)" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "19 18 part4.v(33) " "Warning (10230): Verilog HDL assignment warning at part4.v(33): truncated value with size 19 to match size of target (18)" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data_in part4.v(34) " "Warning (10235): Verilog HDL Always Construct warning at part4.v(34): variable \"Data_in\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 34 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SRAM_data part4.v(35) " "Warning (10235): Verilog HDL Always Construct warning at part4.v(35): variable \"SRAM_data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 35 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:Dis1 " "Info: Elaborating entity \"display\" for hierarchy \"display:Dis1\"" {  } { { "part4.v" "Dis1" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "nCS GND " "Warning (13410): Pin \"nCS\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[8\] GND " "Warning (13410): Pin \"SRAM_add\[8\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[9\] GND " "Warning (13410): Pin \"SRAM_add\[9\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[10\] GND " "Warning (13410): Pin \"SRAM_add\[10\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[11\] GND " "Warning (13410): Pin \"SRAM_add\[11\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[12\] GND " "Warning (13410): Pin \"SRAM_add\[12\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[13\] GND " "Warning (13410): Pin \"SRAM_add\[13\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[14\] GND " "Warning (13410): Pin \"SRAM_add\[14\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[15\] GND " "Warning (13410): Pin \"SRAM_add\[15\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[16\] GND " "Warning (13410): Pin \"SRAM_add\[16\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_add\[17\] GND " "Warning (13410): Pin \"SRAM_add\[17\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_COM\[0\] VCC " "Warning (13410): Pin \"SEG_COM\[0\]\" is stuck at VCC" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_COM\[1\] VCC " "Warning (13410): Pin \"SEG_COM\[1\]\" is stuck at VCC" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_COM\[2\] VCC " "Warning (13410): Pin \"SEG_COM\[2\]\" is stuck at VCC" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_COM\[3\] VCC " "Warning (13410): Pin \"SEG_COM\[3\]\" is stuck at VCC" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEG_DATA\[7\] GND " "Warning (13410): Pin \"SEG_DATA\[7\]\" is stuck at GND" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Sophy/Desktop/LAB_8/part4/part4.map.smsg " "Info: Generated suppressed messages file C:/Users/Sophy/Desktop/LAB_8/part4/part4.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "124 " "Info: Implemented 124 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "38 " "Info: Implemented 38 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "52 " "Info: Implemented 52 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "189 " "Info: Peak virtual memory: 189 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 22 09:34:09 2009 " "Info: Processing ended: Fri May 22 09:34:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}