part4.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 22 09:34:56 2009 " "Info: Processing started: Fri May 22 09:34:56 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off part4 -c part4 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part4 -c part4 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register cnt\[0\] cnt\[1\] 420.17 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 420.17 MHz between source register \"cnt\[0\]\" and destination register \"cnt\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.644 ns + Longest register register " "Info: + Longest register to register delay is 0.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LCFF_X8_Y34_N11 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y34_N11; Fanout = 18; REG Node = 'cnt\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.150 ns) 0.560 ns cnt\[1\]~6 2 COMB LCCOMB_X8_Y34_N16 1 " "Info: 2: + IC(0.410 ns) + CELL(0.150 ns) = 0.560 ns; Loc. = LCCOMB_X8_Y34_N16; Fanout = 1; COMB Node = 'cnt\[1\]~6'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.560 ns" { cnt[0] cnt[1]~6 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.644 ns cnt\[1\] 3 REG LCFF_X8_Y34_N17 12 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.644 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { cnt[1]~6 cnt[1] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 36.34 % ) " "Info: Total cell delay = 0.234 ns ( 36.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.410 ns ( 63.66 % ) " "Info: Total interconnect delay = 0.410 ns ( 63.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.644 ns" { cnt[0] cnt[1]~6 cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.644 ns" { cnt[0] {} cnt[1]~6 {} cnt[1] {} } { 0.000ns 0.410ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.685 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.685 ns cnt\[1\] 3 REG LCFF_X8_Y34_N17 12 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { CLK~clkctrl cnt[1] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[1] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.685 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.685 ns cnt\[0\] 3 REG LCFF_X8_Y34_N11 18 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X8_Y34_N11; Fanout = 18; REG Node = 'cnt\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { CLK~clkctrl cnt[0] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[0] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[1] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[0] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.644 ns" { cnt[0] cnt[1]~6 cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.644 ns" { cnt[0] {} cnt[1]~6 {} cnt[1] {} } { 0.000ns 0.410ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[1] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[0] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { cnt[1] {} } {  } {  } "" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}