prev_cmp_part4.tan.qmsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SEG_DATA\[1\] cnt\[1\] 11.535 ns register " "Info: tco from clock \"CLK\" to destination pin \"SEG_DATA\[1\]\" through register \"cnt\[1\]\" is 11.535 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.685 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns CLK~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 2.685 ns cnt\[1\] 3 REG LCFF_X8_Y34_N17 12 " "Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { CLK~clkctrl cnt[1] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.21 % ) " "Info: Total cell delay = 1.536 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 42.79 % ) " "Info: Total interconnect delay = 1.149 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[1] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[1\] 1 REG LCFF_X8_Y34_N17 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[1] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.275 ns) 0.667 ns Equal1~104 2 COMB LCCOMB_X8_Y34_N0 2 " "Info: 2: + IC(0.392 ns) + CELL(0.275 ns) = 0.667 ns; Loc. = LCCOMB_X8_Y34_N0; Fanout = 2; COMB Node = 'Equal1~104'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.667 ns" { cnt[1] Equal1~104 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.275 ns) 1.383 ns SEG_DATA~3658 3 COMB LCCOMB_X7_Y34_N26 1 " "Info: 3: + IC(0.441 ns) + CELL(0.275 ns) = 1.383 ns; Loc. = LCCOMB_X7_Y34_N26; Fanout = 1; COMB Node = 'SEG_DATA~3658'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.716 ns" { Equal1~104 SEG_DATA~3658 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(0.420 ns) 2.463 ns SEG_DATA~3659 4 COMB LCCOMB_X9_Y34_N20 1 " "Info: 4: + IC(0.660 ns) + CELL(0.420 ns) = 2.463 ns; Loc. = LCCOMB_X9_Y34_N20; Fanout = 1; COMB Node = 'SEG_DATA~3659'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.080 ns" { SEG_DATA~3658 SEG_DATA~3659 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.319 ns) + CELL(2.818 ns) 8.600 ns SEG_DATA\[1\] 5 PIN PIN_AE5 0 " "Info: 5: + IC(3.319 ns) + CELL(2.818 ns) = 8.600 ns; Loc. = PIN_AE5; Fanout = 0; PIN Node = 'SEG_DATA\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.137 ns" { SEG_DATA~3659 SEG_DATA[1] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.788 ns ( 44.05 % ) " "Info: Total cell delay = 3.788 ns ( 44.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.812 ns ( 55.95 % ) " "Info: Total interconnect delay = 4.812 ns ( 55.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { cnt[1] Equal1~104 SEG_DATA~3658 SEG_DATA~3659 SEG_DATA[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { cnt[1] {} Equal1~104 {} SEG_DATA~3658 {} SEG_DATA~3659 {} SEG_DATA[1] {} } { 0.000ns 0.392ns 0.441ns 0.660ns 3.319ns } { 0.000ns 0.275ns 0.275ns 0.420ns 2.818ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.685 ns" { CLK CLK~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.685 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cnt[1] {} } { 0.000ns 0.000ns 0.113ns 1.036ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.600 ns" { cnt[1] Equal1~104 SEG_DATA~3658 SEG_DATA~3659 SEG_DATA[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.600 ns" { cnt[1] {} Equal1~104 {} SEG_DATA~3658 {} SEG_DATA~3659 {} SEG_DATA[1] {} } { 0.000ns 0.392ns 0.441ns 0.660ns 3.319ns } { 0.000ns 0.275ns 0.275ns 0.420ns 2.818ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SRAM_data\[4\] SEG_DATA\[2\] 15.228 ns Longest " "Info: Longest tpd from source pin \"SRAM_data\[4\]\" to destination pin \"SEG_DATA\[2\]\" is 15.228 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SRAM_data\[4\] 1 PIN PIN_B8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_B8; Fanout = 1; PIN Node = 'SRAM_data\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_data[4] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns SRAM_data\[4\]~27 2 COMB IOC_X16_Y36_N1 7 " "Info: 2: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = IOC_X16_Y36_N1; Fanout = 7; COMB Node = 'SRAM_data\[4\]~27'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.850 ns" { SRAM_data[4] SRAM_data[4]~27 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.626 ns) + CELL(0.410 ns) 6.886 ns display:Dis2\|out\[2\]~808 3 COMB LCCOMB_X7_Y34_N6 1 " "Info: 3: + IC(5.626 ns) + CELL(0.410 ns) = 6.886 ns; Loc. = LCCOMB_X7_Y34_N6; Fanout = 1; COMB Node = 'display:Dis2\|out\[2\]~808'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.036 ns" { SRAM_data[4]~27 display:Dis2|out[2]~808 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.420 ns) 7.740 ns SEG_DATA~3660 4 COMB LCCOMB_X8_Y34_N24 1 " "Info: 4: + IC(0.434 ns) + CELL(0.420 ns) = 7.740 ns; Loc. = LCCOMB_X8_Y34_N24; Fanout = 1; COMB Node = 'SEG_DATA~3660'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.854 ns" { display:Dis2|out[2]~808 SEG_DATA~3660 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.275 ns) 8.299 ns SEG_DATA~3661 5 COMB LCCOMB_X8_Y34_N18 1 " "Info: 5: + IC(0.284 ns) + CELL(0.275 ns) = 8.299 ns; Loc. = LCCOMB_X8_Y34_N18; Fanout = 1; COMB Node = 'SEG_DATA~3661'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.559 ns" { SEG_DATA~3660 SEG_DATA~3661 } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.141 ns) + CELL(2.788 ns) 15.228 ns SEG_DATA\[2\] 6 PIN PIN_AD6 0 " "Info: 6: + IC(4.141 ns) + CELL(2.788 ns) = 15.228 ns; Loc. = PIN_AD6; Fanout = 0; PIN Node = 'SEG_DATA\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.929 ns" { SEG_DATA~3661 SEG_DATA[2] } "NODE_NAME" } } { "part4.v" "" { Text "C:/Users/Sophy/Desktop/LAB_8/part4/part4.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.743 ns ( 31.15 % ) " "Info: Total cell delay = 4.743 ns ( 31.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.485 ns ( 68.85 % ) " "Info: Total interconnect delay = 10.485 ns ( 68.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "15.228 ns" { SRAM_data[4] SRAM_data[4]~27 display:Dis2|out[2]~808 SEG_DATA~3660 SEG_DATA~3661 SEG_DATA[2] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "15.228 ns" { SRAM_data[4] {} SRAM_data[4]~27 {} display:Dis2|out[2]~808 {} SEG_DATA~3660 {} SEG_DATA~3661 {} SEG_DATA[2] {} } { 0.000ns 0.000ns 5.626ns 0.434ns 0.284ns 4.141ns } { 0.000ns 0.850ns 0.410ns 0.420ns 0.275ns 2.788ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Peak virtual memory: 150 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 15 11:09:50 2009 " "Info: Processing ended: Fri May 15 11:09:50 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}