part4.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[13]~18 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[13]));
// synopsys translate_off
// defparam \SRAM_data[13]~I .input_async_reset = "none";
// defparam \SRAM_data[13]~I .input_power_up = "low";
// defparam \SRAM_data[13]~I .input_register_mode = "none";
// defparam \SRAM_data[13]~I .input_sync_reset = "none";
// defparam \SRAM_data[13]~I .oe_async_reset = "none";
// defparam \SRAM_data[13]~I .oe_power_up = "low";
// defparam \SRAM_data[13]~I .oe_register_mode = "none";
// defparam \SRAM_data[13]~I .oe_sync_reset = "none";
// defparam \SRAM_data[13]~I .open_drain_output = "true";
// defparam \SRAM_data[13]~I .operation_mode = "bidir";
// defparam \SRAM_data[13]~I .output_async_reset = "none";
// defparam \SRAM_data[13]~I .output_power_up = "low";
// defparam \SRAM_data[13]~I .output_register_mode = "none";
// defparam \SRAM_data[13]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J10
cycloneii_io \SRAM_data[14]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[14]~17 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[14]));
// synopsys translate_off
// defparam \SRAM_data[14]~I .input_async_reset = "none";
// defparam \SRAM_data[14]~I .input_power_up = "low";
// defparam \SRAM_data[14]~I .input_register_mode = "none";
// defparam \SRAM_data[14]~I .input_sync_reset = "none";
// defparam \SRAM_data[14]~I .oe_async_reset = "none";
// defparam \SRAM_data[14]~I .oe_power_up = "low";
// defparam \SRAM_data[14]~I .oe_register_mode = "none";
// defparam \SRAM_data[14]~I .oe_sync_reset = "none";
// defparam \SRAM_data[14]~I .open_drain_output = "true";
// defparam \SRAM_data[14]~I .operation_mode = "bidir";
// defparam \SRAM_data[14]~I .output_async_reset = "none";
// defparam \SRAM_data[14]~I .output_power_up = "low";
// defparam \SRAM_data[14]~I .output_register_mode = "none";
// defparam \SRAM_data[14]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_H10
cycloneii_io \SRAM_data[15]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[15]~16 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[15]));
// synopsys translate_off
// defparam \SRAM_data[15]~I .input_async_reset = "none";
// defparam \SRAM_data[15]~I .input_power_up = "low";
// defparam \SRAM_data[15]~I .input_register_mode = "none";
// defparam \SRAM_data[15]~I .input_sync_reset = "none";
// defparam \SRAM_data[15]~I .oe_async_reset = "none";
// defparam \SRAM_data[15]~I .oe_power_up = "low";
// defparam \SRAM_data[15]~I .oe_register_mode = "none";
// defparam \SRAM_data[15]~I .oe_sync_reset = "none";
// defparam \SRAM_data[15]~I .open_drain_output = "true";
// defparam \SRAM_data[15]~I .operation_mode = "bidir";
// defparam \SRAM_data[15]~I .output_async_reset = "none";
// defparam \SRAM_data[15]~I .output_power_up = "low";
// defparam \SRAM_data[15]~I .output_register_mode = "none";
// defparam \SRAM_data[15]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_W12
cycloneii_io \Data[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[0]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[0]));
// synopsys translate_off
// defparam \Data[0]~I .input_async_reset = "none";
// defparam \Data[0]~I .input_power_up = "low";
// defparam \Data[0]~I .input_register_mode = "none";
// defparam \Data[0]~I .input_sync_reset = "none";
// defparam \Data[0]~I .oe_async_reset = "none";
// defparam \Data[0]~I .oe_power_up = "low";
// defparam \Data[0]~I .oe_register_mode = "none";
// defparam \Data[0]~I .oe_sync_reset = "none";
// defparam \Data[0]~I .operation_mode = "input";
// defparam \Data[0]~I .output_async_reset = "none";
// defparam \Data[0]~I .output_power_up = "low";
// defparam \Data[0]~I .output_register_mode = "none";
// defparam \Data[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_Y10
cycloneii_io \Write~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Write~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Write));
// synopsys translate_off
// defparam \Write~I .input_async_reset = "none";
// defparam \Write~I .input_power_up = "low";
// defparam \Write~I .input_register_mode = "none";
// defparam \Write~I .input_sync_reset = "none";
// defparam \Write~I .oe_async_reset = "none";
// defparam \Write~I .oe_power_up = "low";
// defparam \Write~I .oe_register_mode = "none";
// defparam \Write~I .oe_sync_reset = "none";
// defparam \Write~I .operation_mode = "input";
// defparam \Write~I .output_async_reset = "none";
// defparam \Write~I .output_power_up = "low";
// defparam \Write~I .output_register_mode = "none";
// defparam \Write~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AA11
cycloneii_io \Data[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[1]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[1]));
// synopsys translate_off
// defparam \Data[1]~I .input_async_reset = "none";
// defparam \Data[1]~I .input_power_up = "low";
// defparam \Data[1]~I .input_register_mode = "none";
// defparam \Data[1]~I .input_sync_reset = "none";
// defparam \Data[1]~I .oe_async_reset = "none";
// defparam \Data[1]~I .oe_power_up = "low";
// defparam \Data[1]~I .oe_register_mode = "none";
// defparam \Data[1]~I .oe_sync_reset = "none";
// defparam \Data[1]~I .operation_mode = "input";
// defparam \Data[1]~I .output_async_reset = "none";
// defparam \Data[1]~I .output_power_up = "low";
// defparam \Data[1]~I .output_register_mode = "none";
// defparam \Data[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_Y11
cycloneii_io \Data[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[2]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[2]));
// synopsys translate_off
// defparam \Data[2]~I .input_async_reset = "none";
// defparam \Data[2]~I .input_power_up = "low";
// defparam \Data[2]~I .input_register_mode = "none";
// defparam \Data[2]~I .input_sync_reset = "none";
// defparam \Data[2]~I .oe_async_reset = "none";
// defparam \Data[2]~I .oe_power_up = "low";
// defparam \Data[2]~I .oe_register_mode = "none";
// defparam \Data[2]~I .oe_sync_reset = "none";
// defparam \Data[2]~I .operation_mode = "input";
// defparam \Data[2]~I .output_async_reset = "none";
// defparam \Data[2]~I .output_power_up = "low";
// defparam \Data[2]~I .output_register_mode = "none";
// defparam \Data[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AD11
cycloneii_io \Data[3]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[3]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[3]));
// synopsys translate_off
// defparam \Data[3]~I .input_async_reset = "none";
// defparam \Data[3]~I .input_power_up = "low";
// defparam \Data[3]~I .input_register_mode = "none";
// defparam \Data[3]~I .input_sync_reset = "none";
// defparam \Data[3]~I .oe_async_reset = "none";
// defparam \Data[3]~I .oe_power_up = "low";
// defparam \Data[3]~I .oe_register_mode = "none";
// defparam \Data[3]~I .oe_sync_reset = "none";
// defparam \Data[3]~I .operation_mode = "input";
// defparam \Data[3]~I .output_async_reset = "none";
// defparam \Data[3]~I .output_power_up = "low";
// defparam \Data[3]~I .output_register_mode = "none";
// defparam \Data[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AC11
cycloneii_io \Data[4]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[4]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[4]));
// synopsys translate_off
// defparam \Data[4]~I .input_async_reset = "none";
// defparam \Data[4]~I .input_power_up = "low";
// defparam \Data[4]~I .input_register_mode = "none";
// defparam \Data[4]~I .input_sync_reset = "none";
// defparam \Data[4]~I .oe_async_reset = "none";
// defparam \Data[4]~I .oe_power_up = "low";
// defparam \Data[4]~I .oe_register_mode = "none";
// defparam \Data[4]~I .oe_sync_reset = "none";
// defparam \Data[4]~I .operation_mode = "input";
// defparam \Data[4]~I .output_async_reset = "none";
// defparam \Data[4]~I .output_power_up = "low";
// defparam \Data[4]~I .output_register_mode = "none";
// defparam \Data[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AF10
cycloneii_io \Data[5]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[5]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[5]));
// synopsys translate_off
// defparam \Data[5]~I .input_async_reset = "none";
// defparam \Data[5]~I .input_power_up = "low";
// defparam \Data[5]~I .input_register_mode = "none";
// defparam \Data[5]~I .input_sync_reset = "none";
// defparam \Data[5]~I .oe_async_reset = "none";
// defparam \Data[5]~I .oe_power_up = "low";
// defparam \Data[5]~I .oe_register_mode = "none";
// defparam \Data[5]~I .oe_sync_reset = "none";
// defparam \Data[5]~I .operation_mode = "input";
// defparam \Data[5]~I .output_async_reset = "none";
// defparam \Data[5]~I .output_power_up = "low";
// defparam \Data[5]~I .output_register_mode = "none";
// defparam \Data[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_AE10
cycloneii_io \Data[6]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[6]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[6]));
// synopsys translate_off
// defparam \Data[6]~I .input_async_reset = "none";
// defparam \Data[6]~I .input_power_up = "low";
// defparam \Data[6]~I .input_register_mode = "none";
// defparam \Data[6]~I .input_sync_reset = "none";
// defparam \Data[6]~I .oe_async_reset = "none";
// defparam \Data[6]~I .oe_power_up = "low";
// defparam \Data[6]~I .oe_register_mode = "none";
// defparam \Data[6]~I .oe_sync_reset = "none";
// defparam \Data[6]~I .operation_mode = "input";
// defparam \Data[6]~I .output_async_reset = "none";
// defparam \Data[6]~I .output_power_up = "low";
// defparam \Data[6]~I .output_register_mode = "none";
// defparam \Data[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_W11
cycloneii_io \Data[7]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\Data[7]~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(Data[7]));
// synopsys translate_off
// defparam \Data[7]~I .input_async_reset = "none";
// defparam \Data[7]~I .input_power_up = "low";
// defparam \Data[7]~I .input_register_mode = "none";
// defparam \Data[7]~I .input_sync_reset = "none";
// defparam \Data[7]~I .oe_async_reset = "none";
// defparam \Data[7]~I .oe_power_up = "low";
// defparam \Data[7]~I .oe_register_mode = "none";
// defparam \Data[7]~I .oe_sync_reset = "none";
// defparam \Data[7]~I .operation_mode = "input";
// defparam \Data[7]~I .output_async_reset = "none";
// defparam \Data[7]~I .output_power_up = "low";
// defparam \Data[7]~I .output_register_mode = "none";
// defparam \Data[7]~I .output_sync_reset = "none";
// synopsys translate_on