part4.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// defparam \SRAM_data[1]~I .oe_sync_reset = "none";
// defparam \SRAM_data[1]~I .operation_mode = "bidir";
// defparam \SRAM_data[1]~I .output_async_reset = "none";
// defparam \SRAM_data[1]~I .output_power_up = "low";
// defparam \SRAM_data[1]~I .output_register_mode = "none";
// defparam \SRAM_data[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_D8
cycloneii_io \SRAM_data[2]~I (
	.datain(\Data[2]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[2]~29 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[2]));
// synopsys translate_off
// defparam \SRAM_data[2]~I .input_async_reset = "none";
// defparam \SRAM_data[2]~I .input_power_up = "low";
// defparam \SRAM_data[2]~I .input_register_mode = "none";
// defparam \SRAM_data[2]~I .input_sync_reset = "none";
// defparam \SRAM_data[2]~I .oe_async_reset = "none";
// defparam \SRAM_data[2]~I .oe_power_up = "low";
// defparam \SRAM_data[2]~I .oe_register_mode = "none";
// defparam \SRAM_data[2]~I .oe_sync_reset = "none";
// defparam \SRAM_data[2]~I .operation_mode = "bidir";
// defparam \SRAM_data[2]~I .output_async_reset = "none";
// defparam \SRAM_data[2]~I .output_power_up = "low";
// defparam \SRAM_data[2]~I .output_register_mode = "none";
// defparam \SRAM_data[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_C8
cycloneii_io \SRAM_data[3]~I (
	.datain(\Data[3]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[3]~28 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[3]));
// synopsys translate_off
// defparam \SRAM_data[3]~I .input_async_reset = "none";
// defparam \SRAM_data[3]~I .input_power_up = "low";
// defparam \SRAM_data[3]~I .input_register_mode = "none";
// defparam \SRAM_data[3]~I .input_sync_reset = "none";
// defparam \SRAM_data[3]~I .oe_async_reset = "none";
// defparam \SRAM_data[3]~I .oe_power_up = "low";
// defparam \SRAM_data[3]~I .oe_register_mode = "none";
// defparam \SRAM_data[3]~I .oe_sync_reset = "none";
// defparam \SRAM_data[3]~I .operation_mode = "bidir";
// defparam \SRAM_data[3]~I .output_async_reset = "none";
// defparam \SRAM_data[3]~I .output_power_up = "low";
// defparam \SRAM_data[3]~I .output_register_mode = "none";
// defparam \SRAM_data[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_B8
cycloneii_io \SRAM_data[4]~I (
	.datain(\Data[4]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[4]~27 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[4]));
// synopsys translate_off
// defparam \SRAM_data[4]~I .input_async_reset = "none";
// defparam \SRAM_data[4]~I .input_power_up = "low";
// defparam \SRAM_data[4]~I .input_register_mode = "none";
// defparam \SRAM_data[4]~I .input_sync_reset = "none";
// defparam \SRAM_data[4]~I .oe_async_reset = "none";
// defparam \SRAM_data[4]~I .oe_power_up = "low";
// defparam \SRAM_data[4]~I .oe_register_mode = "none";
// defparam \SRAM_data[4]~I .oe_sync_reset = "none";
// defparam \SRAM_data[4]~I .operation_mode = "bidir";
// defparam \SRAM_data[4]~I .output_async_reset = "none";
// defparam \SRAM_data[4]~I .output_power_up = "low";
// defparam \SRAM_data[4]~I .output_register_mode = "none";
// defparam \SRAM_data[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_A8
cycloneii_io \SRAM_data[5]~I (
	.datain(\Data[5]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[5]~26 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[5]));
// synopsys translate_off
// defparam \SRAM_data[5]~I .input_async_reset = "none";
// defparam \SRAM_data[5]~I .input_power_up = "low";
// defparam \SRAM_data[5]~I .input_register_mode = "none";
// defparam \SRAM_data[5]~I .input_sync_reset = "none";
// defparam \SRAM_data[5]~I .oe_async_reset = "none";
// defparam \SRAM_data[5]~I .oe_power_up = "low";
// defparam \SRAM_data[5]~I .oe_register_mode = "none";
// defparam \SRAM_data[5]~I .oe_sync_reset = "none";
// defparam \SRAM_data[5]~I .operation_mode = "bidir";
// defparam \SRAM_data[5]~I .output_async_reset = "none";
// defparam \SRAM_data[5]~I .output_power_up = "low";
// defparam \SRAM_data[5]~I .output_register_mode = "none";
// defparam \SRAM_data[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K9
cycloneii_io \SRAM_data[6]~I (
	.datain(\Data[6]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[6]~25 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[6]));
// synopsys translate_off
// defparam \SRAM_data[6]~I .input_async_reset = "none";
// defparam \SRAM_data[6]~I .input_power_up = "low";
// defparam \SRAM_data[6]~I .input_register_mode = "none";
// defparam \SRAM_data[6]~I .input_sync_reset = "none";
// defparam \SRAM_data[6]~I .oe_async_reset = "none";
// defparam \SRAM_data[6]~I .oe_power_up = "low";
// defparam \SRAM_data[6]~I .oe_register_mode = "none";
// defparam \SRAM_data[6]~I .oe_sync_reset = "none";
// defparam \SRAM_data[6]~I .operation_mode = "bidir";
// defparam \SRAM_data[6]~I .output_async_reset = "none";
// defparam \SRAM_data[6]~I .output_power_up = "low";
// defparam \SRAM_data[6]~I .output_register_mode = "none";
// defparam \SRAM_data[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J9
cycloneii_io \SRAM_data[7]~I (
	.datain(\Data[7]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[7]~24 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[7]));
// synopsys translate_off
// defparam \SRAM_data[7]~I .input_async_reset = "none";
// defparam \SRAM_data[7]~I .input_power_up = "low";
// defparam \SRAM_data[7]~I .input_register_mode = "none";
// defparam \SRAM_data[7]~I .input_sync_reset = "none";
// defparam \SRAM_data[7]~I .oe_async_reset = "none";
// defparam \SRAM_data[7]~I .oe_power_up = "low";
// defparam \SRAM_data[7]~I .oe_register_mode = "none";
// defparam \SRAM_data[7]~I .oe_sync_reset = "none";
// defparam \SRAM_data[7]~I .operation_mode = "bidir";
// defparam \SRAM_data[7]~I .output_async_reset = "none";
// defparam \SRAM_data[7]~I .output_power_up = "low";
// defparam \SRAM_data[7]~I .output_register_mode = "none";
// defparam \SRAM_data[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_G9
cycloneii_io \SRAM_data[8]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[8]~23 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[8]));
// synopsys translate_off
// defparam \SRAM_data[8]~I .input_async_reset = "none";
// defparam \SRAM_data[8]~I .input_power_up = "low";
// defparam \SRAM_data[8]~I .input_register_mode = "none";
// defparam \SRAM_data[8]~I .input_sync_reset = "none";
// defparam \SRAM_data[8]~I .oe_async_reset = "none";
// defparam \SRAM_data[8]~I .oe_power_up = "low";
// defparam \SRAM_data[8]~I .oe_register_mode = "none";
// defparam \SRAM_data[8]~I .oe_sync_reset = "none";
// defparam \SRAM_data[8]~I .open_drain_output = "true";
// defparam \SRAM_data[8]~I .operation_mode = "bidir";
// defparam \SRAM_data[8]~I .output_async_reset = "none";
// defparam \SRAM_data[8]~I .output_power_up = "low";
// defparam \SRAM_data[8]~I .output_register_mode = "none";
// defparam \SRAM_data[8]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_F9
cycloneii_io \SRAM_data[9]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[9]~22 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[9]));
// synopsys translate_off
// defparam \SRAM_data[9]~I .input_async_reset = "none";
// defparam \SRAM_data[9]~I .input_power_up = "low";
// defparam \SRAM_data[9]~I .input_register_mode = "none";
// defparam \SRAM_data[9]~I .input_sync_reset = "none";
// defparam \SRAM_data[9]~I .oe_async_reset = "none";
// defparam \SRAM_data[9]~I .oe_power_up = "low";
// defparam \SRAM_data[9]~I .oe_register_mode = "none";
// defparam \SRAM_data[9]~I .oe_sync_reset = "none";
// defparam \SRAM_data[9]~I .open_drain_output = "true";
// defparam \SRAM_data[9]~I .operation_mode = "bidir";
// defparam \SRAM_data[9]~I .output_async_reset = "none";
// defparam \SRAM_data[9]~I .output_power_up = "low";
// defparam \SRAM_data[9]~I .output_register_mode = "none";
// defparam \SRAM_data[9]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_D9
cycloneii_io \SRAM_data[10]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[10]~21 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[10]));
// synopsys translate_off
// defparam \SRAM_data[10]~I .input_async_reset = "none";
// defparam \SRAM_data[10]~I .input_power_up = "low";
// defparam \SRAM_data[10]~I .input_register_mode = "none";
// defparam \SRAM_data[10]~I .input_sync_reset = "none";
// defparam \SRAM_data[10]~I .oe_async_reset = "none";
// defparam \SRAM_data[10]~I .oe_power_up = "low";
// defparam \SRAM_data[10]~I .oe_register_mode = "none";
// defparam \SRAM_data[10]~I .oe_sync_reset = "none";
// defparam \SRAM_data[10]~I .open_drain_output = "true";
// defparam \SRAM_data[10]~I .operation_mode = "bidir";
// defparam \SRAM_data[10]~I .output_async_reset = "none";
// defparam \SRAM_data[10]~I .output_power_up = "low";
// defparam \SRAM_data[10]~I .output_register_mode = "none";
// defparam \SRAM_data[10]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_C9
cycloneii_io \SRAM_data[11]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[11]~20 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[11]));
// synopsys translate_off
// defparam \SRAM_data[11]~I .input_async_reset = "none";
// defparam \SRAM_data[11]~I .input_power_up = "low";
// defparam \SRAM_data[11]~I .input_register_mode = "none";
// defparam \SRAM_data[11]~I .input_sync_reset = "none";
// defparam \SRAM_data[11]~I .oe_async_reset = "none";
// defparam \SRAM_data[11]~I .oe_power_up = "low";
// defparam \SRAM_data[11]~I .oe_register_mode = "none";
// defparam \SRAM_data[11]~I .oe_sync_reset = "none";
// defparam \SRAM_data[11]~I .open_drain_output = "true";
// defparam \SRAM_data[11]~I .operation_mode = "bidir";
// defparam \SRAM_data[11]~I .output_async_reset = "none";
// defparam \SRAM_data[11]~I .output_power_up = "low";
// defparam \SRAM_data[11]~I .output_register_mode = "none";
// defparam \SRAM_data[11]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_B9
cycloneii_io \SRAM_data[12]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000001100),
	.combout(\SRAM_data[12]~19 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[12]));
// synopsys translate_off
// defparam \SRAM_data[12]~I .input_async_reset = "none";
// defparam \SRAM_data[12]~I .input_power_up = "low";
// defparam \SRAM_data[12]~I .input_register_mode = "none";
// defparam \SRAM_data[12]~I .input_sync_reset = "none";
// defparam \SRAM_data[12]~I .oe_async_reset = "none";
// defparam \SRAM_data[12]~I .oe_power_up = "low";
// defparam \SRAM_data[12]~I .oe_register_mode = "none";
// defparam \SRAM_data[12]~I .oe_sync_reset = "none";
// defparam \SRAM_data[12]~I .open_drain_output = "true";
// defparam \SRAM_data[12]~I .operation_mode = "bidir";
// defparam \SRAM_data[12]~I .output_async_reset = "none";
// defparam \SRAM_data[12]~I .output_power_up = "low";
// defparam \SRAM_data[12]~I .output_register_mode = "none";
// defparam \SRAM_data[12]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_A9
cycloneii_io \SRAM_data[13]~I (
	.datain(\ALT_INV_Write~combout ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),