part4.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"

// DATE "05/22/2009 09:35:04"

// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This Verilog file should be used for PrimeTime (Verilog) only
// 

`timescale 1 ps/ 1 ps

module part4 (
	CLK,
	Write,
	Address,
	Data,
	SRAM_data,
	nOE,
	nWE,
	nCS,
	SRAM_add,
	LED,
	SEG_COM,
	SEG_DATA);
input 	CLK;
input 	Write;
input 	[7:0] Address;
input 	[7:0] Data;
inout 	[15:0] SRAM_data;
output 	nOE;
output 	nWE;
output 	nCS;
output 	[17:0] SRAM_add;
output 	LED;
output 	[7:0] SEG_COM;
output 	[7:0] SEG_DATA;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("part4_v.sdo");
// synopsys translate_on

wire \Dis1|out[0]~484_combout ;
wire \Dis2|out[1]~807_combout ;
wire \Dis1|out[3]~486_combout ;
wire \SEG_DATA~3667_combout ;
wire \SEG_DATA~3671_combout ;
wire \SEG_DATA~3679_combout ;
wire \CLK~combout ;
wire \CLK~clkctrl_outclk ;
wire \SRAM_data[0]~31 ;
wire \SRAM_data[1]~30 ;
wire \SRAM_data[2]~29 ;
wire \SRAM_data[3]~28 ;
wire \SRAM_data[4]~27 ;
wire \SRAM_data[5]~26 ;
wire \SRAM_data[6]~25 ;
wire \SRAM_data[7]~24 ;
wire \SRAM_data[8]~23 ;
wire \SRAM_data[9]~22 ;
wire \SRAM_data[10]~21 ;
wire \SRAM_data[11]~20 ;
wire \SRAM_data[12]~19 ;
wire \SRAM_data[13]~18 ;
wire \SRAM_data[14]~17 ;
wire \SRAM_data[15]~16 ;
wire \Data[0]~combout ;
wire \Write~combout ;
wire \Data[1]~combout ;
wire \Data[2]~combout ;
wire \Data[3]~combout ;
wire \Data[4]~combout ;
wire \Data[5]~combout ;
wire \Data[6]~combout ;
wire \Data[7]~combout ;
wire \Address[0]~combout ;
wire \Address[1]~combout ;
wire \Address[2]~combout ;
wire \Address[3]~combout ;
wire \Address[4]~combout ;
wire \Address[5]~combout ;
wire \Address[6]~combout ;
wire \Address[7]~combout ;
wire \cnt[0]~7_combout ;
wire \cnt[0]~regout ;
wire \cnt[1]~6_combout ;
wire \cnt[1]~regout ;
wire \Equal1~102_combout ;
wire \Equal1~103_combout ;
wire \Equal1~104_combout ;
wire \SEG_DATA~3651_combout ;
wire \Dis2|out[0]~806_combout ;
wire \Dis3|out[0]~806_combout ;
wire \SEG_DATA~3652_combout ;
wire \Dis4|out[0]~806_combout ;
wire \SEG_DATA~3653_combout ;
wire \Dis3|out[1]~807_combout ;
wire \SEG_DATA~3656_combout ;
wire \SEG_DATA~3658_combout ;
wire \SEG_DATA~3654_combout ;
wire \SEG_DATA~3655_combout ;
wire \Dis4|out[1]~807_combout ;
wire \SEG_DATA~3657_combout ;
wire \SEG_DATA~3659_combout ;
wire \Dis1|out[2]~485_combout ;
wire \Dis3|out[2]~808_combout ;
wire \Dis2|out[2]~808_combout ;
wire \Dis4|out[2]~808_combout ;
wire \SEG_DATA~3660_combout ;
wire \SEG_DATA~3661_combout ;
wire \Dis2|out[3]~809_combout ;
wire \Dis3|out[3]~809_combout ;
wire \SEG_DATA~3662_combout ;
wire \Dis4|out[3]~809_combout ;
wire \SEG_DATA~3663_combout ;
wire \SEG_DATA~3665_combout ;
wire \SEG_DATA~3666_combout ;
wire \SEG_DATA~3668_combout ;
wire \SEG_DATA~3664_combout ;
wire \SEG_DATA~3669_combout ;
wire \SEG_DATA~3672_combout ;
wire \SEG_DATA~3673_combout ;
wire \SEG_DATA~3674_combout ;
wire \SEG_DATA~3670_combout ;
wire \SEG_DATA~3682_combout ;
wire \SEG_DATA~3675_combout ;
wire \SEG_DATA~3678_combout ;
wire \SEG_DATA~3680_combout ;
wire \SEG_DATA~3677_combout ;
wire \SEG_DATA~3676_combout ;
wire \SEG_DATA~3681_combout ;

wire \ALT_INV_Equal1~102_combout ;
wire \ALT_INV_Equal1~103_combout ;
wire \ALT_INV_Equal1~104_combout ;
wire \ALT_INV_SEG_DATA~3651_combout ;
wire \ALT_INV_Write~combout ;

INV \INV_INST_Equal1~102_combout  (
	.IN1(\Equal1~102_combout ),
	.Y(\ALT_INV_Equal1~102_combout ));

INV \INV_INST_Equal1~103_combout  (
	.IN1(\Equal1~103_combout ),
	.Y(\ALT_INV_Equal1~103_combout ));

INV \INV_INST_Equal1~104_combout  (
	.IN1(\Equal1~104_combout ),
	.Y(\ALT_INV_Equal1~104_combout ));

INV \INV_INST_SEG_DATA~3651_combout  (
	.IN1(\SEG_DATA~3651_combout ),
	.Y(\ALT_INV_SEG_DATA~3651_combout ));

INV \INV_INST_Write~combout  (
	.IN1(\Write~combout ),
	.Y(\ALT_INV_Write~combout ));

// atom is at LCCOMB_X7_Y34_N10
cycloneii_lcell_comb \Dis1|out[0]~484 (
// Equation(s):
// \Dis1|out[0]~484_combout  = \SRAM_data[1]~30  & (\SRAM_data[2]~29  # !\SRAM_data[0]~31  # !\SRAM_data[3]~28 ) # !\SRAM_data[1]~30  & (\SRAM_data[2]~29  $ (\SRAM_data[3]~28  # !\SRAM_data[0]~31 ))

	.dataa(\SRAM_data[3]~28 ),
	.datab(\SRAM_data[0]~31 ),
	.datac(\SRAM_data[1]~30 ),
	.datad(\SRAM_data[2]~29 ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis1|out[0]~484_combout ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis1|out[0]~484 .lut_mask = 16'hF47B;
// defparam \Dis1|out[0]~484 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X7_Y34_N24
cycloneii_lcell_comb \Dis2|out[1]~807 (
// Equation(s):
// \Dis2|out[1]~807_combout  = \SRAM_data[6]~25  & (\SRAM_data[4]~27  $ \SRAM_data[7]~24  $ !\SRAM_data[5]~26 ) # !\SRAM_data[6]~25  & (!\SRAM_data[5]~26  # !\SRAM_data[7]~24  # !\SRAM_data[4]~27 )

	.dataa(\SRAM_data[4]~27 ),
	.datab(\SRAM_data[6]~25 ),
	.datac(\SRAM_data[7]~24 ),
	.datad(\SRAM_data[5]~26 ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis2|out[1]~807_combout ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis2|out[1]~807 .lut_mask = 16'h5BB7;
// defparam \Dis2|out[1]~807 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X7_Y34_N2
cycloneii_lcell_comb \Dis1|out[3]~486 (
// Equation(s):
// \Dis1|out[3]~486_combout  = \SRAM_data[1]~30  & (!\SRAM_data[2]~29  # !\SRAM_data[0]~31 ) # !\SRAM_data[1]~30  & (\SRAM_data[3]~28  # \SRAM_data[0]~31  $ !\SRAM_data[2]~29 )

	.dataa(\SRAM_data[3]~28 ),
	.datab(\SRAM_data[0]~31 ),
	.datac(\SRAM_data[1]~30 ),
	.datad(\SRAM_data[2]~29 ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis1|out[3]~486_combout ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis1|out[3]~486 .lut_mask = 16'h3EFB;
// defparam \Dis1|out[3]~486 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X7_Y34_N14
cycloneii_lcell_comb \SEG_DATA~3667 (
// Equation(s):
// \SEG_DATA~3667_combout  = \SRAM_data[5]~26  & (\SRAM_data[7]~24  # !\SRAM_data[4]~27 ) # !\SRAM_data[5]~26  & (\SRAM_data[6]~25  & (\SRAM_data[7]~24 ) # !\SRAM_data[6]~25  & !\SRAM_data[4]~27 )

	.dataa(\SRAM_data[4]~27 ),
	.datab(\SRAM_data[6]~25 ),
	.datac(\SRAM_data[7]~24 ),
	.datad(\SRAM_data[5]~26 ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\SEG_DATA~3667_combout ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \SEG_DATA~3667 .lut_mask = 16'hF5D1;
// defparam \SEG_DATA~3667 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X7_Y34_N8
cycloneii_lcell_comb \SEG_DATA~3671 (
// Equation(s):
// \SEG_DATA~3671_combout  = \SRAM_data[6]~25  & (\SRAM_data[5]~26  # !\SRAM_data[7]~24 ) # !\SRAM_data[6]~25  & (\SRAM_data[4]~27  & \SRAM_data[7]~24  # !\SRAM_data[4]~27  & (!\SRAM_data[5]~26 ))

	.dataa(\SRAM_data[4]~27 ),
	.datab(\SRAM_data[6]~25 ),
	.datac(\SRAM_data[7]~24 ),
	.datad(\SRAM_data[5]~26 ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\SEG_DATA~3671_combout ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \SEG_DATA~3671 .lut_mask = 16'hEC3D;
// defparam \SEG_DATA~3671 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X7_Y34_N30
cycloneii_lcell_comb \SEG_DATA~3679 (
// Equation(s):
// \SEG_DATA~3679_combout  = \SRAM_data[7]~24  # \SRAM_data[6]~25  & (!\SRAM_data[5]~26  # !\SRAM_data[4]~27 ) # !\SRAM_data[6]~25  & (\SRAM_data[5]~26 )

	.dataa(\SRAM_data[4]~27 ),
	.datab(\SRAM_data[6]~25 ),
	.datac(\SRAM_data[7]~24 ),
	.datad(\SRAM_data[5]~26 ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\SEG_DATA~3679_combout ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \SEG_DATA~3679 .lut_mask = 16'hF7FC;
// defparam \SEG_DATA~3679 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_N1
cycloneii_io \CLK~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000001),
	.combout(\CLK~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(CLK));
// synopsys translate_off
// defparam \CLK~I .input_async_reset = "none";
// defparam \CLK~I .input_power_up = "low";
// defparam \CLK~I .input_register_mode = "none";
// defparam \CLK~I .input_sync_reset = "none";
// defparam \CLK~I .oe_async_reset = "none";
// defparam \CLK~I .oe_power_up = "low";
// defparam \CLK~I .oe_register_mode = "none";
// defparam \CLK~I .oe_sync_reset = "none";
// defparam \CLK~I .operation_mode = "input";
// defparam \CLK~I .output_async_reset = "none";
// defparam \CLK~I .output_power_up = "low";
// defparam \CLK~I .output_register_mode = "none";
// defparam \CLK~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G2
cycloneii_clkctrl \CLK~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\CLK~combout }),
	.clkselect(2'b00),
	.modesel(1'b0),
	.outclk(\CLK~clkctrl_outclk ));
// synopsys translate_off
// defparam \CLK~clkctrl .clock_type = "global clock";
// defparam \CLK~clkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_H8
cycloneii_io \SRAM_data[0]~I (
	.datain(\Data[0]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[0]~31 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[0]));
// synopsys translate_off
// defparam \SRAM_data[0]~I .input_async_reset = "none";
// defparam \SRAM_data[0]~I .input_power_up = "low";
// defparam \SRAM_data[0]~I .input_register_mode = "none";
// defparam \SRAM_data[0]~I .input_sync_reset = "none";
// defparam \SRAM_data[0]~I .oe_async_reset = "none";
// defparam \SRAM_data[0]~I .oe_power_up = "low";
// defparam \SRAM_data[0]~I .oe_register_mode = "none";
// defparam \SRAM_data[0]~I .oe_sync_reset = "none";
// defparam \SRAM_data[0]~I .operation_mode = "bidir";
// defparam \SRAM_data[0]~I .output_async_reset = "none";
// defparam \SRAM_data[0]~I .output_power_up = "low";
// defparam \SRAM_data[0]~I .output_register_mode = "none";
// defparam \SRAM_data[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_E8
cycloneii_io \SRAM_data[1]~I (
	.datain(\Data[1]~combout ),
	.oe(\Write~combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.modesel(26'b00000000000000000000000100),
	.combout(\SRAM_data[1]~30 ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(SRAM_data[1]));
// synopsys translate_off
// defparam \SRAM_data[1]~I .input_async_reset = "none";
// defparam \SRAM_data[1]~I .input_power_up = "low";
// defparam \SRAM_data[1]~I .input_register_mode = "none";
// defparam \SRAM_data[1]~I .input_sync_reset = "none";
// defparam \SRAM_data[1]~I .oe_async_reset = "none";
// defparam \SRAM_data[1]~I .oe_power_up = "low";
// defparam \SRAM_data[1]~I .oe_register_mode = "none";