part4.v

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

module part4(CLK, Write, Address, Data, SRAM_data, 
			 nOE, nWE, nCS, SRAM_add, LED, SEG_COM, SEG_DATA);
	input CLK, Write; 
	input [7:0] Address;
	input [7:0] Data;
	inout [15:0] SRAM_data;
	output nOE, nWE, nCS; 
	output [17:0] SRAM_add;
	output LED;
	output [7:0] SEG_COM, SEG_DATA;	

	wire [7:0] Seg1, Seg2, Seg3, Seg4;
	reg [17:0] Address_in;
	wire [15:0] Q, Data_in;

	reg [1:0] cnt;	
	reg [15:0] in;	
	reg [15:0] out; 

	assign Data_in = {9'b000000000, Data};

	assign SRAM_data = Write? in : 15'bZ;
	assign SRAM_add = Address_in;
	assign nCS = 0;
	assign nWE = ~Write;
	assign nOE = Write;
	
	always@(posedge CLK) begin
		cnt = cnt+1;
	end
	
	always@(Address or Data) begin
		Address_in = {11'b00000000000, Address};
		in <= Data_in;
		out <= SRAM_data;
	end

	assign Q = out;

	display Dis1 (Q[3:0], Seg1);
	display Dis2 (Q[7:4], Seg2);
	display Dis3 (Q[11:8], Seg3);
	display Dis4 (Q[15:12], Seg4);	
	
	assign LED = Write;
	
	assign SEG_COM = (cnt==0)?8'b01111111:
					 (cnt==1)?8'b10111111:
					 (cnt==2)?8'b11011111:
					 (cnt==3)?8'b11101111:8'b11111111;
					
	assign SEG_DATA = (cnt==0)?Seg1:
					  (cnt==1)?Seg2:
					  (cnt==2)?Seg3:
					  (cnt==3)?Seg4:8'b00000000;

endmodule

module display(in,out);
	input [3:0] in;
	output [7:0] out;
	
	assign out = (in==0)?8'b00111111:
				 (in==1)?8'b00000110:
				 (in==2)?8'b01011011:
				 (in==3)?8'b01001111:
				 (in==4)?8'b01100110:
				 (in==5)?8'b01101101:
				 (in==6)?8'b01111101:
				 (in==7)?8'b00100111:
				 (in==8)?8'b01111111:
				 (in==9)?8'b01101111:
				 (in==10)?8'b01011111:
				 (in==11)?8'b01111100:
				 (in==12)?8'b01011000:
				 (in==13)?8'b01011110:
				 (in==14)?8'b01111011:
				 (in==15)?8'b01110001:8'b00000000;
			
endmodule