📄 part4.tan.rpt
字号:
; N/A ; None ; 13.941 ns ; SRAM_data[0] ; SEG_DATA[2] ;
; N/A ; None ; 13.881 ns ; SRAM_data[14] ; SEG_DATA[1] ;
; N/A ; None ; 13.875 ns ; SRAM_data[10] ; SEG_DATA[1] ;
; N/A ; None ; 13.866 ns ; SRAM_data[0] ; SEG_DATA[1] ;
; N/A ; None ; 13.853 ns ; SRAM_data[1] ; SEG_DATA[0] ;
; N/A ; None ; 13.847 ns ; SRAM_data[9] ; SEG_DATA[2] ;
; N/A ; None ; 13.836 ns ; SRAM_data[1] ; SEG_DATA[2] ;
; N/A ; None ; 13.830 ns ; SRAM_data[13] ; SEG_DATA[0] ;
; N/A ; None ; 13.827 ns ; SRAM_data[3] ; SEG_DATA[6] ;
; N/A ; None ; 13.783 ns ; SRAM_data[12] ; SEG_DATA[0] ;
; N/A ; None ; 13.743 ns ; SRAM_data[1] ; SEG_DATA[1] ;
; N/A ; None ; 13.731 ns ; SRAM_data[4] ; SEG_DATA[5] ;
; N/A ; None ; 13.697 ns ; SRAM_data[8] ; SEG_DATA[2] ;
; N/A ; None ; 13.675 ns ; SRAM_data[14] ; SEG_DATA[0] ;
; N/A ; None ; 13.664 ns ; SRAM_data[5] ; SEG_DATA[0] ;
; N/A ; None ; 13.654 ns ; SRAM_data[5] ; SEG_DATA[4] ;
; N/A ; None ; 13.606 ns ; SRAM_data[9] ; SEG_DATA[1] ;
; N/A ; None ; 13.550 ns ; SRAM_data[15] ; SEG_DATA[4] ;
; N/A ; None ; 13.525 ns ; SRAM_data[2] ; SEG_DATA[6] ;
; N/A ; None ; 13.453 ns ; SRAM_data[8] ; SEG_DATA[1] ;
; N/A ; None ; 13.427 ns ; SRAM_data[3] ; SEG_DATA[5] ;
; N/A ; None ; 13.374 ns ; SRAM_data[15] ; SEG_DATA[1] ;
; N/A ; None ; 13.333 ns ; SRAM_data[5] ; SEG_DATA[5] ;
; N/A ; None ; 13.329 ns ; SRAM_data[0] ; SEG_DATA[6] ;
; N/A ; None ; 13.316 ns ; SRAM_data[6] ; SEG_DATA[0] ;
; N/A ; None ; 13.302 ns ; SRAM_data[6] ; SEG_DATA[4] ;
; N/A ; None ; 13.287 ns ; SRAM_data[3] ; SEG_DATA[4] ;
; N/A ; None ; 13.267 ns ; SRAM_data[11] ; SEG_DATA[6] ;
; N/A ; None ; 13.224 ns ; SRAM_data[11] ; SEG_DATA[3] ;
; N/A ; None ; 13.213 ns ; SRAM_data[11] ; SEG_DATA[4] ;
; N/A ; None ; 13.207 ns ; SRAM_data[1] ; SEG_DATA[6] ;
; N/A ; None ; 13.174 ns ; SRAM_data[7] ; SEG_DATA[4] ;
; N/A ; None ; 13.172 ns ; SRAM_data[7] ; SEG_DATA[0] ;
; N/A ; None ; 13.149 ns ; SRAM_data[15] ; SEG_DATA[0] ;
; N/A ; None ; 13.124 ns ; SRAM_data[2] ; SEG_DATA[5] ;
; N/A ; None ; 13.072 ns ; SRAM_data[10] ; SEG_DATA[6] ;
; N/A ; None ; 13.039 ns ; SRAM_data[3] ; SEG_DATA[3] ;
; N/A ; None ; 13.031 ns ; SRAM_data[10] ; SEG_DATA[3] ;
; N/A ; None ; 13.021 ns ; SRAM_data[10] ; SEG_DATA[4] ;
; N/A ; None ; 12.984 ns ; SRAM_data[2] ; SEG_DATA[4] ;
; N/A ; None ; 12.983 ns ; SRAM_data[6] ; SEG_DATA[5] ;
; N/A ; None ; 12.933 ns ; SRAM_data[0] ; SEG_DATA[5] ;
; N/A ; None ; 12.932 ns ; SRAM_data[8] ; SEG_DATA[6] ;
; N/A ; None ; 12.889 ns ; SRAM_data[8] ; SEG_DATA[3] ;
; N/A ; None ; 12.875 ns ; SRAM_data[8] ; SEG_DATA[4] ;
; N/A ; None ; 12.850 ns ; SRAM_data[7] ; SEG_DATA[5] ;
; N/A ; None ; 12.795 ns ; SRAM_data[1] ; SEG_DATA[5] ;
; N/A ; None ; 12.791 ns ; SRAM_data[0] ; SEG_DATA[4] ;
; N/A ; None ; 12.736 ns ; SRAM_data[2] ; SEG_DATA[3] ;
; N/A ; None ; 12.734 ns ; SRAM_data[4] ; SEG_DATA[3] ;
; N/A ; None ; 12.666 ns ; SRAM_data[1] ; SEG_DATA[4] ;
; N/A ; None ; 12.654 ns ; SRAM_data[11] ; SEG_DATA[5] ;
; N/A ; None ; 12.563 ns ; SRAM_data[13] ; SEG_DATA[5] ;
; N/A ; None ; 12.544 ns ; SRAM_data[0] ; SEG_DATA[3] ;
; N/A ; None ; 12.505 ns ; SRAM_data[12] ; SEG_DATA[5] ;
; N/A ; None ; 12.458 ns ; SRAM_data[9] ; SEG_DATA[6] ;
; N/A ; None ; 12.421 ns ; SRAM_data[1] ; SEG_DATA[3] ;
; N/A ; None ; 12.417 ns ; SRAM_data[9] ; SEG_DATA[3] ;
; N/A ; None ; 12.408 ns ; SRAM_data[9] ; SEG_DATA[4] ;
; N/A ; None ; 12.396 ns ; SRAM_data[13] ; SEG_DATA[3] ;
; N/A ; None ; 12.386 ns ; SRAM_data[14] ; SEG_DATA[5] ;
; N/A ; None ; 12.349 ns ; SRAM_data[12] ; SEG_DATA[3] ;
; N/A ; None ; 12.329 ns ; SRAM_data[10] ; SEG_DATA[5] ;
; N/A ; None ; 12.329 ns ; SRAM_data[5] ; SEG_DATA[3] ;
; N/A ; None ; 12.241 ns ; SRAM_data[14] ; SEG_DATA[3] ;
; N/A ; None ; 12.059 ns ; SRAM_data[9] ; SEG_DATA[5] ;
; N/A ; None ; 11.972 ns ; SRAM_data[6] ; SEG_DATA[3] ;
; N/A ; None ; 11.904 ns ; SRAM_data[8] ; SEG_DATA[5] ;
; N/A ; None ; 11.883 ns ; SRAM_data[15] ; SEG_DATA[5] ;
; N/A ; None ; 11.865 ns ; SRAM_data[7] ; SEG_DATA[3] ;
; N/A ; None ; 11.715 ns ; SRAM_data[15] ; SEG_DATA[3] ;
; N/A ; None ; 10.898 ns ; Write ; SRAM_data[12] ;
; N/A ; None ; 10.898 ns ; Write ; SRAM_data[13] ;
; N/A ; None ; 10.730 ns ; Write ; SRAM_data[8] ;
; N/A ; None ; 10.730 ns ; Write ; SRAM_data[9] ;
; N/A ; None ; 10.730 ns ; Write ; SRAM_data[15] ;
; N/A ; None ; 10.519 ns ; Write ; SRAM_data[0] ;
; N/A ; None ; 10.500 ns ; Address[2] ; SRAM_add[2] ;
; N/A ; None ; 10.499 ns ; Write ; SRAM_data[7] ;
; N/A ; None ; 10.499 ns ; Write ; SRAM_data[6] ;
; N/A ; None ; 10.479 ns ; Write ; SRAM_data[1] ;
; N/A ; None ; 10.433 ns ; Write ; SRAM_data[10] ;
; N/A ; None ; 10.433 ns ; Write ; SRAM_data[11] ;
; N/A ; None ; 10.432 ns ; Data[7] ; SRAM_data[7] ;
; N/A ; None ; 10.411 ns ; Write ; SRAM_data[5] ;
; N/A ; None ; 10.411 ns ; Write ; SRAM_data[4] ;
; N/A ; None ; 10.401 ns ; Write ; nWE ;
; N/A ; None ; 10.401 ns ; Write ; nOE ;
; N/A ; None ; 10.384 ns ; Address[6] ; SRAM_add[6] ;
; N/A ; None ; 10.349 ns ; Address[7] ; SRAM_add[7] ;
; N/A ; None ; 10.340 ns ; Address[5] ; SRAM_add[5] ;
; N/A ; None ; 10.335 ns ; Address[3] ; SRAM_add[3] ;
; N/A ; None ; 10.238 ns ; Write ; SRAM_data[14] ;
; N/A ; None ; 10.155 ns ; Address[0] ; SRAM_add[0] ;
; N/A ; None ; 10.143 ns ; Data[3] ; SRAM_data[3] ;
; N/A ; None ; 10.140 ns ; Data[1] ; SRAM_data[1] ;
; N/A ; None ; 10.136 ns ; Write ; SRAM_data[2] ;
; N/A ; None ; 10.136 ns ; Write ; SRAM_data[3] ;
; N/A ; None ; 10.118 ns ; Address[4] ; SRAM_add[4] ;
; N/A ; None ; 10.107 ns ; Data[0] ; SRAM_data[0] ;
; N/A ; None ; 10.104 ns ; Data[5] ; SRAM_data[5] ;
; N/A ; None ; 10.087 ns ; Data[6] ; SRAM_data[6] ;
; N/A ; None ; 9.936 ns ; Data[2] ; SRAM_data[2] ;
; N/A ; None ; 9.870 ns ; Data[4] ; SRAM_data[4] ;
; N/A ; None ; 9.810 ns ; Address[1] ; SRAM_add[1] ;
; N/A ; None ; 9.108 ns ; Write ; LED ;
+-------+-------------------+-----------------+---------------+---------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Fri May 22 09:34:56 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part4 -c part4 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 420.17 MHz between source register "cnt[0]" and destination register "cnt[1]"
Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.644 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y34_N11; Fanout = 18; REG Node = 'cnt[0]'
Info: 2: + IC(0.410 ns) + CELL(0.150 ns) = 0.560 ns; Loc. = LCCOMB_X8_Y34_N16; Fanout = 1; COMB Node = 'cnt[1]~6'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.644 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt[1]'
Info: Total cell delay = 0.234 ns ( 36.34 % )
Info: Total interconnect delay = 0.410 ns ( 63.66 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 2.685 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt[1]'
Info: Total cell delay = 1.536 ns ( 57.21 % )
Info: Total interconnect delay = 1.149 ns ( 42.79 % )
Info: - Longest clock path from clock "CLK" to source register is 2.685 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X8_Y34_N11; Fanout = 18; REG Node = 'cnt[0]'
Info: Total cell delay = 1.536 ns ( 57.21 % )
Info: Total interconnect delay = 1.149 ns ( 42.79 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "CLK" to destination pin "SEG_DATA[1]" through register "cnt[1]" is 11.535 ns
Info: + Longest clock path from clock "CLK" to source register is 2.685 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(1.036 ns) + CELL(0.537 ns) = 2.685 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt[1]'
Info: Total cell delay = 1.536 ns ( 57.21 % )
Info: Total interconnect delay = 1.149 ns ( 42.79 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Longest register to pin delay is 8.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y34_N17; Fanout = 12; REG Node = 'cnt[1]'
Info: 2: + IC(0.392 ns) + CELL(0.275 ns) = 0.667 ns; Loc. = LCCOMB_X8_Y34_N0; Fanout = 2; COMB Node = 'Equal1~104'
Info: 3: + IC(0.441 ns) + CELL(0.275 ns) = 1.383 ns; Loc. = LCCOMB_X7_Y34_N26; Fanout = 1; COMB Node = 'SEG_DATA~3658'
Info: 4: + IC(0.660 ns) + CELL(0.420 ns) = 2.463 ns; Loc. = LCCOMB_X9_Y34_N20; Fanout = 1; COMB Node = 'SEG_DATA~3659'
Info: 5: + IC(3.319 ns) + CELL(2.818 ns) = 8.600 ns; Loc. = PIN_AE5; Fanout = 0; PIN Node = 'SEG_DATA[1]'
Info: Total cell delay = 3.788 ns ( 44.05 % )
Info: Total interconnect delay = 4.812 ns ( 55.95 % )
Info: Longest tpd from source pin "SRAM_data[4]" to destination pin "SEG_DATA[2]" is 15.228 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_B8; Fanout = 1; PIN Node = 'SRAM_data[4]'
Info: 2: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = IOC_X16_Y36_N1; Fanout = 7; COMB Node = 'SRAM_data[4]~27'
Info: 3: + IC(5.626 ns) + CELL(0.410 ns) = 6.886 ns; Loc. = LCCOMB_X7_Y34_N6; Fanout = 1; COMB Node = 'display:Dis2|out[2]~808'
Info: 4: + IC(0.434 ns) + CELL(0.420 ns) = 7.740 ns; Loc. = LCCOMB_X8_Y34_N24; Fanout = 1; COMB Node = 'SEG_DATA~3660'
Info: 5: + IC(0.284 ns) + CELL(0.275 ns) = 8.299 ns; Loc. = LCCOMB_X8_Y34_N18; Fanout = 1; COMB Node = 'SEG_DATA~3661'
Info: 6: + IC(4.141 ns) + CELL(2.788 ns) = 15.228 ns; Loc. = PIN_AD6; Fanout = 0; PIN Node = 'SEG_DATA[2]'
Info: Total cell delay = 4.743 ns ( 31.15 % )
Info: Total interconnect delay = 10.485 ns ( 68.85 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 150 megabytes
Info: Processing ended: Fri May 22 09:34:58 2009
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
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