part4_modelsim.xrf

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

vendor_name = ModelSim
source_file = 1, part4
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part4/part4.vwf
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part4/part4.v
source_file = 1, C:/Users/Sophy/Desktop/LAB_8/part4/db/part4.cbx.xml
design_name = part4
instance = comp, \Dis1|out[0]~484 , Dis1|out[0]~484, part4, 1
instance = comp, \Dis2|out[1]~807 , Dis2|out[1]~807, part4, 1
instance = comp, \Dis1|out[3]~486 , Dis1|out[3]~486, part4, 1
instance = comp, \SEG_DATA~3667 , SEG_DATA~3667, part4, 1
instance = comp, \SEG_DATA~3671 , SEG_DATA~3671, part4, 1
instance = comp, \SEG_DATA~3679 , SEG_DATA~3679, part4, 1
instance = comp, \CLK~I , CLK, part4, 1
instance = comp, \CLK~clkctrl , CLK~clkctrl, part4, 1
instance = comp, \SRAM_data[0]~I , SRAM_data[0], part4, 1
instance = comp, \SRAM_data[1]~I , SRAM_data[1], part4, 1
instance = comp, \SRAM_data[2]~I , SRAM_data[2], part4, 1
instance = comp, \SRAM_data[3]~I , SRAM_data[3], part4, 1
instance = comp, \SRAM_data[4]~I , SRAM_data[4], part4, 1
instance = comp, \SRAM_data[5]~I , SRAM_data[5], part4, 1
instance = comp, \SRAM_data[6]~I , SRAM_data[6], part4, 1
instance = comp, \SRAM_data[7]~I , SRAM_data[7], part4, 1
instance = comp, \SRAM_data[8]~I , SRAM_data[8], part4, 1
instance = comp, \SRAM_data[9]~I , SRAM_data[9], part4, 1
instance = comp, \SRAM_data[10]~I , SRAM_data[10], part4, 1
instance = comp, \SRAM_data[11]~I , SRAM_data[11], part4, 1
instance = comp, \SRAM_data[12]~I , SRAM_data[12], part4, 1
instance = comp, \SRAM_data[13]~I , SRAM_data[13], part4, 1
instance = comp, \SRAM_data[14]~I , SRAM_data[14], part4, 1
instance = comp, \SRAM_data[15]~I , SRAM_data[15], part4, 1
instance = comp, \Data[0]~I , Data[0], part4, 1
instance = comp, \Write~I , Write, part4, 1
instance = comp, \Data[1]~I , Data[1], part4, 1
instance = comp, \Data[2]~I , Data[2], part4, 1
instance = comp, \Data[3]~I , Data[3], part4, 1
instance = comp, \Data[4]~I , Data[4], part4, 1
instance = comp, \Data[5]~I , Data[5], part4, 1
instance = comp, \Data[6]~I , Data[6], part4, 1
instance = comp, \Data[7]~I , Data[7], part4, 1
instance = comp, \Address[0]~I , Address[0], part4, 1
instance = comp, \Address[1]~I , Address[1], part4, 1
instance = comp, \Address[2]~I , Address[2], part4, 1
instance = comp, \Address[3]~I , Address[3], part4, 1
instance = comp, \Address[4]~I , Address[4], part4, 1
instance = comp, \Address[5]~I , Address[5], part4, 1
instance = comp, \Address[6]~I , Address[6], part4, 1
instance = comp, \Address[7]~I , Address[7], part4, 1
instance = comp, \cnt[0]~7 , cnt[0]~7, part4, 1
instance = comp, \cnt[0] , cnt[0], part4, 1
instance = comp, \cnt[1]~6 , cnt[1]~6, part4, 1
instance = comp, \cnt[1] , cnt[1], part4, 1
instance = comp, \Equal1~102 , Equal1~102, part4, 1
instance = comp, \Equal1~103 , Equal1~103, part4, 1
instance = comp, \Equal1~104 , Equal1~104, part4, 1
instance = comp, \SEG_DATA~3651 , SEG_DATA~3651, part4, 1
instance = comp, \Dis2|out[0]~806 , Dis2|out[0]~806, part4, 1
instance = comp, \Dis3|out[0]~806 , Dis3|out[0]~806, part4, 1
instance = comp, \SEG_DATA~3652 , SEG_DATA~3652, part4, 1
instance = comp, \Dis4|out[0]~806 , Dis4|out[0]~806, part4, 1
instance = comp, \SEG_DATA~3653 , SEG_DATA~3653, part4, 1
instance = comp, \Dis3|out[1]~807 , Dis3|out[1]~807, part4, 1
instance = comp, \SEG_DATA~3656 , SEG_DATA~3656, part4, 1
instance = comp, \SEG_DATA~3658 , SEG_DATA~3658, part4, 1
instance = comp, \SEG_DATA~3654 , SEG_DATA~3654, part4, 1
instance = comp, \SEG_DATA~3655 , SEG_DATA~3655, part4, 1
instance = comp, \Dis4|out[1]~807 , Dis4|out[1]~807, part4, 1
instance = comp, \SEG_DATA~3657 , SEG_DATA~3657, part4, 1
instance = comp, \SEG_DATA~3659 , SEG_DATA~3659, part4, 1
instance = comp, \Dis1|out[2]~485 , Dis1|out[2]~485, part4, 1
instance = comp, \Dis3|out[2]~808 , Dis3|out[2]~808, part4, 1
instance = comp, \Dis2|out[2]~808 , Dis2|out[2]~808, part4, 1
instance = comp, \Dis4|out[2]~808 , Dis4|out[2]~808, part4, 1
instance = comp, \SEG_DATA~3660 , SEG_DATA~3660, part4, 1
instance = comp, \SEG_DATA~3661 , SEG_DATA~3661, part4, 1
instance = comp, \Dis2|out[3]~809 , Dis2|out[3]~809, part4, 1
instance = comp, \Dis3|out[3]~809 , Dis3|out[3]~809, part4, 1
instance = comp, \SEG_DATA~3662 , SEG_DATA~3662, part4, 1
instance = comp, \Dis4|out[3]~809 , Dis4|out[3]~809, part4, 1
instance = comp, \SEG_DATA~3663 , SEG_DATA~3663, part4, 1
instance = comp, \SEG_DATA~3665 , SEG_DATA~3665, part4, 1
instance = comp, \SEG_DATA~3666 , SEG_DATA~3666, part4, 1
instance = comp, \SEG_DATA~3668 , SEG_DATA~3668, part4, 1
instance = comp, \SEG_DATA~3664 , SEG_DATA~3664, part4, 1
instance = comp, \SEG_DATA~3669 , SEG_DATA~3669, part4, 1
instance = comp, \SEG_DATA~3672 , SEG_DATA~3672, part4, 1
instance = comp, \SEG_DATA~3673 , SEG_DATA~3673, part4, 1
instance = comp, \SEG_DATA~3674 , SEG_DATA~3674, part4, 1
instance = comp, \SEG_DATA~3670 , SEG_DATA~3670, part4, 1
instance = comp, \SEG_DATA~3682 , SEG_DATA~3682, part4, 1
instance = comp, \SEG_DATA~3675 , SEG_DATA~3675, part4, 1
instance = comp, \SEG_DATA~3678 , SEG_DATA~3678, part4, 1
instance = comp, \SEG_DATA~3680 , SEG_DATA~3680, part4, 1
instance = comp, \SEG_DATA~3677 , SEG_DATA~3677, part4, 1
instance = comp, \SEG_DATA~3676 , SEG_DATA~3676, part4, 1
instance = comp, \SEG_DATA~3681 , SEG_DATA~3681, part4, 1
instance = comp, \nOE~I , nOE, part4, 1
instance = comp, \nWE~I , nWE, part4, 1
instance = comp, \nCS~I , nCS, part4, 1
instance = comp, \SRAM_add[0]~I , SRAM_add[0], part4, 1
instance = comp, \SRAM_add[1]~I , SRAM_add[1], part4, 1
instance = comp, \SRAM_add[2]~I , SRAM_add[2], part4, 1
instance = comp, \SRAM_add[3]~I , SRAM_add[3], part4, 1
instance = comp, \SRAM_add[4]~I , SRAM_add[4], part4, 1
instance = comp, \SRAM_add[5]~I , SRAM_add[5], part4, 1
instance = comp, \SRAM_add[6]~I , SRAM_add[6], part4, 1
instance = comp, \SRAM_add[7]~I , SRAM_add[7], part4, 1
instance = comp, \SRAM_add[8]~I , SRAM_add[8], part4, 1
instance = comp, \SRAM_add[9]~I , SRAM_add[9], part4, 1
instance = comp, \SRAM_add[10]~I , SRAM_add[10], part4, 1
instance = comp, \SRAM_add[11]~I , SRAM_add[11], part4, 1
instance = comp, \SRAM_add[12]~I , SRAM_add[12], part4, 1
instance = comp, \SRAM_add[13]~I , SRAM_add[13], part4, 1
instance = comp, \SRAM_add[14]~I , SRAM_add[14], part4, 1
instance = comp, \SRAM_add[15]~I , SRAM_add[15], part4, 1
instance = comp, \SRAM_add[16]~I , SRAM_add[16], part4, 1
instance = comp, \SRAM_add[17]~I , SRAM_add[17], part4, 1
instance = comp, \LED~I , LED, part4, 1
instance = comp, \SEG_COM[0]~I , SEG_COM[0], part4, 1
instance = comp, \SEG_COM[1]~I , SEG_COM[1], part4, 1
instance = comp, \SEG_COM[2]~I , SEG_COM[2], part4, 1
instance = comp, \SEG_COM[3]~I , SEG_COM[3], part4, 1
instance = comp, \SEG_COM[4]~I , SEG_COM[4], part4, 1
instance = comp, \SEG_COM[5]~I , SEG_COM[5], part4, 1
instance = comp, \SEG_COM[6]~I , SEG_COM[6], part4, 1
instance = comp, \SEG_COM[7]~I , SEG_COM[7], part4, 1
instance = comp, \SEG_DATA[0]~I , SEG_DATA[0], part4, 1
instance = comp, \SEG_DATA[1]~I , SEG_DATA[1], part4, 1
instance = comp, \SEG_DATA[2]~I , SEG_DATA[2], part4, 1
instance = comp, \SEG_DATA[3]~I , SEG_DATA[3], part4, 1
instance = comp, \SEG_DATA[4]~I , SEG_DATA[4], part4, 1
instance = comp, \SEG_DATA[5]~I , SEG_DATA[5], part4, 1
instance = comp, \SEG_DATA[6]~I , SEG_DATA[6], part4, 1
instance = comp, \SEG_DATA[7]~I , SEG_DATA[7], part4, 1