part4.map.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                         ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path               ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------+
; part4.v                          ; yes             ; Auto-Found Verilog HDL File  ; C:/Users/Sophy/Desktop/LAB_8/part4/part4.v ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 52    ;
;                                             ;       ;
; Total combinational functions               ; 52    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 45    ;
;     -- 3 input functions                    ; 1     ;
;     -- <=2 input functions                  ; 6     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 52    ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 2     ;
;     -- Dedicated logic registers            ; 2     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 72    ;
; Maximum fan-out node                        ; Write ;
; Maximum fan-out                             ; 19    ;
; Total fan-out                               ; 244   ;
; Average fan-out                             ; 1.94  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |part4                     ; 52 (37)           ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 72   ; 0            ; |part4              ; work         ;
;    |display:Dis1|          ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part4|display:Dis1 ; work         ;
;    |display:Dis2|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part4|display:Dis2 ; work         ;
;    |display:Dis3|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part4|display:Dis3 ; work         ;
;    |display:Dis4|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part4|display:Dis4 ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Fri May 22 09:33:52 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part4 -c part4
Warning: Using design file part4.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: part4
    Info: Found entity 2: display
Info: Elaborating entity "part4" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at part4.v(20): truncated value with size 17 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at part4.v(29): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at part4.v(33): truncated value with size 19 to match size of target (18)
Warning (10235): Verilog HDL Always Construct warning at part4.v(34): variable "Data_in" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at part4.v(35): variable "SRAM_data" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Elaborating entity "display" for hierarchy "display:Dis1"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "nCS" is stuck at GND
    Warning (13410): Pin "SRAM_add[8]" is stuck at GND
    Warning (13410): Pin "SRAM_add[9]" is stuck at GND
    Warning (13410): Pin "SRAM_add[10]" is stuck at GND
    Warning (13410): Pin "SRAM_add[11]" is stuck at GND
    Warning (13410): Pin "SRAM_add[12]" is stuck at GND
    Warning (13410): Pin "SRAM_add[13]" is stuck at GND
    Warning (13410): Pin "SRAM_add[14]" is stuck at GND
    Warning (13410): Pin "SRAM_add[15]" is stuck at GND
    Warning (13410): Pin "SRAM_add[16]" is stuck at GND
    Warning (13410): Pin "SRAM_add[17]" is stuck at GND
    Warning (13410): Pin "SEG_COM[0]" is stuck at VCC
    Warning (13410): Pin "SEG_COM[1]" is stuck at VCC
    Warning (13410): Pin "SEG_COM[2]" is stuck at VCC
    Warning (13410): Pin "SEG_COM[3]" is stuck at VCC
    Warning (13410): Pin "SEG_DATA[7]" is stuck at GND
Info: Generated suppressed messages file C:/Users/Sophy/Desktop/LAB_8/part4/part4.map.smsg
Info: Implemented 124 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 38 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 52 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings
    Info: Peak virtual memory: 189 megabytes
    Info: Processing ended: Fri May 22 09:34:09 2009
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:06


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Users/Sophy/Desktop/LAB_8/part4/part4.map.smsg.