part3.map.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                           ;
+----------------------------------+-----------------+------------------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path       ;
+----------------------------------+-----------------+------------------------+------------------------------------+
; part3.v                          ; yes             ; User Verilog HDL File  ; C:/altera/72sp2/LAB8/part3/part3.v ;
+----------------------------------+-----------------+------------------------+------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 303   ;
;                                             ;       ;
; Total combinational functions               ; 303   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 245   ;
;     -- 3 input functions                    ; 53    ;
;     -- <=2 input functions                  ; 5     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 303   ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 259   ;
;     -- Dedicated logic registers            ; 259   ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 33    ;
; Maximum fan-out node                        ; Clock ;
; Maximum fan-out                             ; 256   ;
; Total fan-out                               ; 1938  ;
; Average fan-out                             ; 3.26  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |part3                     ; 303 (95)          ; 259 (3)      ; 0           ; 0            ; 0       ; 0         ; 33   ; 0            ; |part3              ; work         ;
;    |display:Dis1|          ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part3|display:Dis1 ; work         ;
;    |display:Dis3|          ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part3|display:Dis3 ; work         ;
;    |display:Dis4|          ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part3|display:Dis4 ; work         ;
;    |display:Dis5|          ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part3|display:Dis5 ; work         ;
;    |display:Dis6|          ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part3|display:Dis6 ; work         ;
;    |myram:Ram|             ; 184 (184)         ; 256 (256)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |part3|myram:Ram    ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 259   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 256   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition
    Info: Processing started: Fri May 09 19:47:40 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part3 -c part3
Info: Found 3 design units, including 3 entities, in source file part3.v
    Info: Found entity 1: part3
    Info: Found entity 2: myram
    Info: Found entity 3: display
Info: Elaborating entity "part3" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at part3.v(17): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "myram" for hierarchy "myram:Ram"
Info: Elaborating entity "display" for hierarchy "display:Dis1"
Info: Found 1 instances of uninferred RAM logic
    Info: RAM logic "myram:Ram|memory_array" uninferred due to asynchronous read logic
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "SEG_DATA[7]" stuck at GND
Info: Implemented 592 device resources after synthesis - the final resource count might be different
    Info: Implemented 16 input pins
    Info: Implemented 17 output pins
    Info: Implemented 559 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 144 megabytes of memory during processing
    Info: Processing ended: Fri May 09 19:47:48 2008
    Info: Elapsed time: 00:00:08