part3.v.bak

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

module part3(CLK, SW_A, Address, Data, Wren, LED, SEG_COM, SEG_DATA);
	input CLK, SW_A, Wren; //SW_A->Clock input
	input [4:0] Address; 	//DIP_D[12:8]
	input [7:0] Data; 		//DIP_D[7:0]
	output LED; 			//Wren 钎矫
	output [7:0] SEG_COM, SEG_DATA; //SEG7,8->address value seg4,5->input data
									//seg1,2->read out of the memory
									
	wire Clock;
	wire [3:0] Add;
	wire [7:0] Q, Seg_Add_Value1, Seg_Add_Value2, Seg_input_Value1, Seg_input_Value2,
				  Seg_Read_Value1, Seg_Read_Value2;
				
	reg [2:0] cnt;
	
	always@(posedge CLK) begin
		cnt = cnt+1;
	end
	
	myram Ram (Address, Clock, Data, Wren, Q);
	
	assign Add = {3'b000, Address[0]};
	
	display Dis1 (Address[3:0], Seg_Add_Value1);
	display Dis2 (Add, Seg_Add_Value2);
	display Dis3 (Data[3:0], Seg_input_Value1);
	display Dis4 (Data[7:4], Seg_input_Value2);
	display Dis5 (Q[3:0], Seg_Read_Value1);
	display Dis6 (Q[7:4], Seg_Read_Value2);

	assign Clock = SW_A & CLK; 
	assign LED = Wren;
	
	assign SEG_COM = (cnt==0)?8'b01111111:
					 (cnt==1)?8'b10111111:
					 (cnt==2)?8'b11011111:
					 (cnt==3)?8'b11101111:
					 (cnt==4)?8'b11110111:
					 (cnt==5)?8'b11111011:
					 (cnt==6)?8'b11111101:
					 (cnt==7)?8'b11111110:8'b11111111;
					
	assign SEG_DATA = (cnt==0)?Seg_Add_Value1:
					  (cnt==1)?Seg_Add_Value2:
					  (cnt==2)?8'b00000000:
					  (cnt==3)?Seg_input_Value1:
					  (cnt==4)?Seg_input_Value2:
					  (cnt==5)?8'b00000000:
					  (cnt==6)?Seg_Read_Value1:
					  (cnt==7)?Seg_Read_Value2:8'b00000000;
endmodule

module myram(Address, CLK, Data, Wren, Q);
	input CLK, Wren;
	input [4:0] Address;
	input [7:0] Data;
	output [7:0] Q;
	
	reg [7:0] memory_array[31:0];
	
	always@(posedge CLK) begin
		if(Wren == 1) begin
			memory_array[Address] = Data;
		end		
	end
	
	assign Q = memory_array[Address];	
endmodule

module display(in,out);
	input [3:0] in;
	output [7:0] out;
	
	assign out[0] = (~in[2]&~in[0])|(in[3]&~in[2]&~in[1])|(~in[3]&in[2]&in[0])|(in[2]&in[1])|(~in[3]&in[1]);
	assign out[1] = (~in[3]&~in[1]&~in[0])|(~in[2]&~in[1])|(in[3]&~in[1]&in[0])|(in[3]&in[1]&~in[0])|(~in[3]&in[1]&in[0])|(~in[3]&~in[2]);
	assign out[2] = (~in[1]&in[0])|(in[3]&~in[2])|(~in[3]&in[2])|(~in[3]&~in[2]&in[0])|(~in[3]&~in[2]&~in[1]);
	assign out[3] = (in[2]&~in[1]&in[0])|(in[3]&~in[1])|(~in[2]&in[1]&in[0])|(in[2]&in[1]&~in[0])|(~in[3]&~in[2]&~in[0]);
	assign out[4] = (~in[2]&~in[0])|(in[3]&in[1])|(in[1]&~in[0])|(in[3]&in[2]);
	assign out[5] = (~in[3]&in[2])|(in[3]&~in[2])|(~in[3]&~in[1]&~in[0])|(in[3]&in[1]);
	assign out[6] = in[3]|(in[1]&~in[0])|(in[2]&~in[1])|(~in[2]&in[1]);
	assign out[7] = 0;
endmodule