part2.v

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

module part2(CLK, SW_A, Address, Data, Wren, LED, SEG_COM, SEG_DATA);
	input CLK, SW_A, Wren; //SW_A->Clock input
	input [4:0] Address; 	//DIP_D[12:8]
	input [7:0] Data; 		//DIP_D[7:0]
	
	output LED; 			//Wren 钎矫
	output [7:0] SEG_COM, SEG_DATA; //SEG7,8->address value seg4,5->input data
									//seg1,2->read out of the memory
	wire Clock;
	wire [3:0] Add;
	wire [7:0] Q, Seg_Add_Value1, Seg_Add_Value2, Seg_input_Value1, Seg_input_Value2,
				  Seg_Read_Value1, Seg_Read_Value2;
				
	reg [2:0] cnt;
	
	always@(posedge CLK) begin
		cnt = cnt+1;
	end
	
	myram Ram (Address, Clock, Data, Wren, Q);
	
	assign Add = {3'b000, Address[4]};
	
	display Dis1 (Address[3:0], Seg_Add_Value1);
	display Dis2 (Add, Seg_Add_Value2);
	display Dis3 (Data[3:0], Seg_input_Value1);
	display Dis4 (Data[7:4], Seg_input_Value2);
	display Dis5 (Q[3:0], Seg_Read_Value1);
	display Dis6 (Q[7:4], Seg_Read_Value2);

	assign Clock = SW_A & CLK; 
	assign LED = Wren;
	
	assign SEG_COM = (cnt==0)?8'b01111111:
					 (cnt==1)?8'b10111111:
					 (cnt==2)?8'b11011111:
					 (cnt==3)?8'b11101111:
					 (cnt==4)?8'b11110111:
					 (cnt==5)?8'b11111011:
					 (cnt==6)?8'b11111101:
					 (cnt==7)?8'b11111110:8'b11111111;
					
	assign SEG_DATA = (cnt==0)?Seg_Add_Value1:
					  (cnt==1)?Seg_Add_Value2:
					  (cnt==2)?8'b00000000:
					  (cnt==3)?Seg_input_Value1:
					  (cnt==4)?Seg_input_Value2:
					  (cnt==5)?8'b00000000:
					  (cnt==6)?Seg_Read_Value1:
					  (cnt==7)?Seg_Read_Value2:8'b00000000;
endmodule

module myram (address, clock, data, wren, q);
	input	[4:0]  address;
	input	  clock;
	input	[7:0]  data;
	input	  wren;
	output	[7:0]  q;

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.wren_a (wren),
				.clock0 (clock),
				.address_a (address),
				.data_a (data),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.intended_device_family = "Cyclone II",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 32,
		altsyncram_component.operation_mode = "SINGLE_PORT",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.ram_block_type = "M4K",
		altsyncram_component.widthad_a = 5,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_byteena_a = 1;
endmodule

module display(in,out);
	input [3:0] in;
	output [7:0] out;
	
	assign out[0] = (~in[2]&~in[0])|(in[3]&~in[2]&~in[1])|(~in[3]&in[2]&in[0])|(in[2]&in[1])|(~in[3]&in[1]);
	assign out[1] = (~in[3]&~in[1]&~in[0])|(~in[2]&~in[1])|(in[3]&~in[1]&in[0])|(in[3]&in[1]&~in[0])|(~in[3]&in[1]&in[0])|(~in[3]&~in[2]);
	assign out[2] = (~in[1]&in[0])|(in[3]&~in[2])|(~in[3]&in[2])|(~in[3]&~in[2]&in[0])|(~in[3]&~in[2]&~in[1]);
	assign out[3] = (in[2]&~in[1]&in[0])|(in[3]&~in[1])|(~in[2]&in[1]&in[0])|(in[2]&in[1]&~in[0])|(~in[3]&~in[2]&~in[0]);
	assign out[4] = (~in[2]&~in[0])|(in[3]&in[1])|(in[1]&~in[0])|(in[3]&in[2]);
	assign out[5] = (~in[3]&in[2])|(in[3]&~in[2])|(~in[3]&~in[1]&~in[0])|(in[3]&in[1]);
	assign out[6] = in[3]|(in[1]&~in[0])|(in[2]&~in[1])|(~in[2]&in[1]);
	assign out[7] = 0;
endmodule