part2.vo

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

// DATE "06/04/2007 12:51:43"

// 
// Device: Altera EP2C35F672C6 Package FBGA672
// 

// 
// This Verilog file should be used for PrimeTime (Verilog) only
// 

`timescale 1 ps/ 1 ps

module part2 (
	CLK,
	SW_A,
	Address,
	Data,
	Wren,
	LED,
	SEG_COM,
	SEG_DATA);
input 	CLK;
input 	SW_A;
input 	[4:0] Address;
input 	[7:0] Data;
input 	Wren;
output 	LED;
output 	[7:0] SEG_COM;
output 	[7:0] SEG_DATA;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("part2_v.sdo");
// synopsys translate_on

wire \Ram|altsyncram_component|auto_generated|q_a[0] ;
wire \Ram|altsyncram_component|auto_generated|q_a[6] ;
wire \Dis3|out[0]~577 ;
wire \Dis5|out[1]~797 ;
wire \Dis6|out[1]~803 ;
wire \Dis4|out[2]~535 ;
wire \Dis6|out[2]~804 ;
wire \Dis5|out[3]~799 ;
wire \SEG_DATA~6300 ;
wire \Dis6|out[5] ;
wire \Dis4|out[6]~536 ;
wire \SEG_DATA~6317 ;
wire \SEG_DATA~6318 ;
wire \CLK~clkctrl ;
wire \Wren~combout ;
wire \cnt[0]~112 ;
wire \cnt[0] ;
wire \cnt[1]~111 ;
wire \cnt[1] ;
wire \cnt[2]~110 ;
wire \cnt[2] ;
wire \Equal0~136 ;
wire \SEG_COM~64 ;
wire \SEG_COM~65 ;
wire \Equal0~137 ;
wire \Equal0~138 ;
wire \Equal0~139 ;
wire \Equal0~140 ;
wire \Equal0~141 ;
wire \SW_A~combout ;
wire \CLK~combout ;
wire Clock;
wire \Clock~clkctrl ;
wire \Data[0]~combout ;
wire \Address[0]~combout ;
wire \Address[1]~combout ;
wire \Address[2]~combout ;
wire \Address[3]~combout ;
wire \Address[4]~combout ;
wire \Data[1]~combout ;
wire \Data[2]~combout ;
wire \Data[3]~combout ;
wire \Data[4]~combout ;
wire \Data[5]~combout ;
wire \Data[6]~combout ;
wire \Data[7]~combout ;
wire \Ram|altsyncram_component|auto_generated|q_a[5] ;
wire \Ram|altsyncram_component|auto_generated|q_a[7] ;
wire \Ram|altsyncram_component|auto_generated|q_a[4] ;
wire \Dis6|out[0]~802 ;
wire \Equal0~142 ;
wire \SEG_DATA~6281 ;
wire \SEG_DATA~6280 ;
wire \Ram|altsyncram_component|auto_generated|q_a[3] ;
wire \Ram|altsyncram_component|auto_generated|q_a[2] ;
wire \Ram|altsyncram_component|auto_generated|q_a[1] ;
wire \Dis5|out[0]~796 ;
wire \SEG_DATA~6282 ;
wire \SEG_DATA~6283 ;
wire \SEG_DATA~6284 ;
wire \SEG_DATA~6285 ;
wire \SEG_DATA~6286 ;
wire \SEG_DATA~6287 ;
wire \SEG_DATA~6324 ;
wire \Equal0~143 ;
wire \Dis4|out[1]~534 ;
wire \SEG_DATA~6288 ;
wire \SEG_DATA~6276 ;
wire \SEG_DATA~6323 ;
wire \SEG_DATA~6289 ;
wire \SEG_DATA~6290 ;
wire \SEG_DATA~6291 ;
wire \SEG_DATA~6292 ;
wire \SEG_DATA~6325 ;
wire \SEG_DATA~6293 ;
wire \Dis5|out[2]~798 ;
wire \SEG_DATA~6294 ;
wire \SEG_DATA~6322 ;
wire \SEG_DATA~6295 ;
wire \SEG_DATA~6296 ;
wire \SEG_DATA~6297 ;
wire \Dis6|out[3]~805 ;
wire \SEG_DATA~6279 ;
wire \SEG_DATA~6298 ;
wire \Dis3|out[3]~578 ;
wire \SEG_DATA~6299 ;
wire \SEG_DATA~6301 ;
wire \SEG_DATA~6302 ;
wire \SEG_DATA~6303 ;
wire \Dis6|out[4]~806 ;
wire \Dis5|out[4]~800 ;
wire \SEG_DATA~6304 ;
wire \Dis3|out[4]~579 ;
wire \SEG_DATA~6305 ;
wire \SEG_DATA~6306 ;
wire \SEG_DATA~6307 ;
wire \SEG_DATA~6308 ;
wire \SEG_DATA~6309 ;
wire \SEG_DATA~6313 ;
wire \SEG_DATA~6312 ;
wire \SEG_DATA~6314 ;
wire \Dis3|out[5]~580 ;
wire \Dis5|out[5] ;
wire \SEG_DATA~6310 ;
wire \SEG_DATA~6311 ;
wire \SEG_DATA~6315 ;
wire \Dis5|out[6]~801 ;
wire \Dis6|out[6]~807 ;
wire \SEG_DATA~6319 ;
wire \SEG_DATA~6320 ;
wire \SEG_DATA~6316 ;
wire \SEG_DATA~6321 ;

wire \ALT_INV_Equal0~136 ;
wire \ALT_INV_SEG_COM~65 ;
wire \ALT_INV_Equal0~137 ;
wire \ALT_INV_Equal0~138 ;
wire \ALT_INV_Equal0~139 ;
wire \ALT_INV_Equal0~140 ;
wire \ALT_INV_Equal0~141 ;
wire [143:0] \Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

AND1 \Ram|altsyncram_component|auto_generated|q_a[0]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[0] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[1]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[1] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[2]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[2] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[3]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[3] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[4]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[4] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[5]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[5] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[6]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[6] ));

AND1 \Ram|altsyncram_component|auto_generated|q_a[7]pt_buf (
	.IN1(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]),
	.Y(\Ram|altsyncram_component|auto_generated|q_a[7] ));


INV \INV_INST_Equal0~136  (
	.IN1(\Equal0~136 ),
	.Y(\ALT_INV_Equal0~136 ));

INV \INV_INST_SEG_COM~65  (
	.IN1(\SEG_COM~65 ),
	.Y(\ALT_INV_SEG_COM~65 ));

INV \INV_INST_Equal0~137  (
	.IN1(\Equal0~137 ),
	.Y(\ALT_INV_Equal0~137 ));

INV \INV_INST_Equal0~138  (
	.IN1(\Equal0~138 ),
	.Y(\ALT_INV_Equal0~138 ));

INV \INV_INST_Equal0~139  (
	.IN1(\Equal0~139 ),
	.Y(\ALT_INV_Equal0~139 ));

INV \INV_INST_Equal0~140  (
	.IN1(\Equal0~140 ),
	.Y(\ALT_INV_Equal0~140 ));

INV \INV_INST_Equal0~141  (
	.IN1(\Equal0~141 ),
	.Y(\ALT_INV_Equal0~141 ));

// atom is at M4K_X13_Y3
cycloneii_ram_block \Ram|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(\Wren~combout ),
	.portaaddrstall(gnd),
	.portbrewe(vcc),
	.portbaddrstall(gnd),
	.clk0(\Clock~clkctrl ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\Data[7]~combout ,\Data[6]~combout ,\Data[5]~combout ,\Data[4]~combout ,\Data[3]~combout ,\Data[2]~combout ,
\Data[1]~combout ,\Data[0]~combout }),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\Address[4]~combout ,\Address[3]~combout ,\Address[2]~combout ,\Address[1]~combout ,\Address[0]~combout }),
	.portabyteenamasks(16'b1111111111111111),
	.portbdatain(72'b000000000000000000000000000000000000000000000000000000000000000000000000),
	.portbaddr(16'b0000000000000000),
	.portbbyteenamasks(16'b1111111111111111),
	.modesel(49'b0000000111000100000000000000000000000000000000001),
	.portadataout(\Ram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ALTSYNCRAM";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 5;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 31;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 5;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 8;
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M4K";
// defparam \Ram|altsyncram_component|auto_generated|ram_block1a0 .safe_write = "err_on_2clk";
// synopsys translate_on

// atom is at LCCOMB_X11_Y3_N10
cycloneii_lcell_comb \Dis3|out[0]~577_I (
// Equation(s):
// \Dis3|out[0]~577  = \Data[2]~combout  & (\Data[1]~combout  # \Data[0]~combout  & !\Data[3]~combout ) # !\Data[2]~combout  & (\Data[3]~combout  $ \Data[1]~combout  # !\Data[0]~combout )

	.dataa(\Data[0]~combout ),
	.datab(\Data[2]~combout ),
	.datac(\Data[3]~combout ),
	.datad(\Data[1]~combout ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis3|out[0]~577 ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis3|out[0]~577_I .lut_mask = 16'hDF39;
// defparam \Dis3|out[0]~577_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X12_Y3_N2
cycloneii_lcell_comb \Dis5|out[1]~797_I (
// Equation(s):
// \Dis5|out[1]~797  = \Ram|altsyncram_component|auto_generated|q_a[2]  & (\Ram|altsyncram_component|auto_generated|q_a[0]  $ \Ram|altsyncram_component|auto_generated|q_a[3]  $ !\Ram|altsyncram_component|auto_generated|q_a[1] ) # 
// !\Ram|altsyncram_component|auto_generated|q_a[2]  & (!\Ram|altsyncram_component|auto_generated|q_a[1]  # !\Ram|altsyncram_component|auto_generated|q_a[3]  # !\Ram|altsyncram_component|auto_generated|q_a[0] )

	.dataa(\Ram|altsyncram_component|auto_generated|q_a[0] ),
	.datab(\Ram|altsyncram_component|auto_generated|q_a[3] ),
	.datac(\Ram|altsyncram_component|auto_generated|q_a[2] ),
	.datad(\Ram|altsyncram_component|auto_generated|q_a[1] ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis5|out[1]~797 ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis5|out[1]~797_I .lut_mask = 16'h679F;
// defparam \Dis5|out[1]~797_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X6_Y3_N0
cycloneii_lcell_comb \Dis6|out[1]~803_I (
// Equation(s):
// \Dis6|out[1]~803  = \Ram|altsyncram_component|auto_generated|q_a[6]  & (\Ram|altsyncram_component|auto_generated|q_a[7]  $ \Ram|altsyncram_component|auto_generated|q_a[5]  $ !\Ram|altsyncram_component|auto_generated|q_a[4] ) # 
// !\Ram|altsyncram_component|auto_generated|q_a[6]  & (!\Ram|altsyncram_component|auto_generated|q_a[4]  # !\Ram|altsyncram_component|auto_generated|q_a[5]  # !\Ram|altsyncram_component|auto_generated|q_a[7] )

	.dataa(\Ram|altsyncram_component|auto_generated|q_a[6] ),
	.datab(\Ram|altsyncram_component|auto_generated|q_a[7] ),
	.datac(\Ram|altsyncram_component|auto_generated|q_a[5] ),
	.datad(\Ram|altsyncram_component|auto_generated|q_a[4] ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis6|out[1]~803 ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis6|out[1]~803_I .lut_mask = 16'h3DD7;
// defparam \Dis6|out[1]~803_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X8_Y3_N24
cycloneii_lcell_comb \Dis4|out[2]~535_I (
// Equation(s):
// \Dis4|out[2]~535  = \Data[6]~combout  & (!\Data[5]~combout  & \Data[4]~combout  # !\Data[7]~combout ) # !\Data[6]~combout  & (\Data[4]~combout  # \Data[7]~combout  # !\Data[5]~combout )

	.dataa(\Data[5]~combout ),
	.datab(\Data[4]~combout ),
	.datac(\Data[6]~combout ),
	.datad(\Data[7]~combout ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis4|out[2]~535 ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis4|out[2]~535_I .lut_mask = 16'h4FFD;
// defparam \Dis4|out[2]~535_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X6_Y3_N6
cycloneii_lcell_comb \Dis6|out[2]~804_I (
// Equation(s):
// \Dis6|out[2]~804  = \Ram|altsyncram_component|auto_generated|q_a[6]  & (!\Ram|altsyncram_component|auto_generated|q_a[5]  & \Ram|altsyncram_component|auto_generated|q_a[4]  # !\Ram|altsyncram_component|auto_generated|q_a[7] ) # 
// !\Ram|altsyncram_component|auto_generated|q_a[6]  & (\Ram|altsyncram_component|auto_generated|q_a[7]  # \Ram|altsyncram_component|auto_generated|q_a[4]  # !\Ram|altsyncram_component|auto_generated|q_a[5] )

	.dataa(\Ram|altsyncram_component|auto_generated|q_a[6] ),
	.datab(\Ram|altsyncram_component|auto_generated|q_a[7] ),
	.datac(\Ram|altsyncram_component|auto_generated|q_a[5] ),
	.datad(\Ram|altsyncram_component|auto_generated|q_a[4] ),
	.cin(gnd),
	.modesel(4'b1001),
	.combout(\Dis6|out[2]~804 ),
	.cout(),
	.pathsel(8'b00001111));
// synopsys translate_off
// defparam \Dis6|out[2]~804_I .lut_mask = 16'h7F67;
// defparam \Dis6|out[2]~804_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X12_Y3_N24
cycloneii_lcell_comb \Dis5|out[3]~799_I (
// Equation(s):
// \Dis5|out[3]~799  = \Ram|altsyncram_component|auto_generated|q_a[1]  & (\Ram|altsyncram_component|auto_generated|q_a[0]  & (!\Ram|altsyncram_component|auto_generated|q_a[2] ) # !\Ram|altsyncram_component|auto_generated|q_a[0]  & 
// (\Ram|altsyncram_component|auto_generated|q_a[2]  # !\Ram|altsyncram_component|auto_generated|q_a[3] )) # !\Ram|altsyncram_component|auto_generated|q_a[1]  & (\Ram|altsyncram_component|auto_generated|q_a[3]  # 
// \Ram|altsyncram_component|auto_generated|q_a[0]  $ !\Ram|altsyncram_component|auto_generated|q_a[2] )

	.dataa(\Ram|altsyncram_component|auto_generated|q_a[0] ),
	.datab(\Ram|altsyncram_component|auto_generated|q_a[3] ),
	.datac(\Ram|altsyncram_component|auto_generated|q_a[2] ),