part2.map.smsg

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat May 26 19:25:10 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part2 -c part2
Error (10170): Verilog HDL syntax error at part2.v(10) near text "wire";  expecting ";", or "," File: D:/傈傍/3切斥1切扁/叼瘤判角氰/Quartus/角嚼12/2/part2.v Line: 10
Error (10170): Verilog HDL syntax error at part2.v(34) near text "assign";  expecting ";", or "," File: D:/傈傍/3切斥1切扁/叼瘤判角氰/Quartus/角嚼12/2/part2.v Line: 34
Error (10112): Ignored design unit "part2" at part2.v(1) due to previous errors File: D:/傈傍/3切斥1切扁/叼瘤判角氰/Quartus/角嚼12/2/part2.v Line: 1
Error (10112): Ignored design unit "myram" at part2.v(53) due to previous errors File: D:/傈傍/3切斥1切扁/叼瘤判角氰/Quartus/角嚼12/2/part2.v Line: 53
Error (10112): Ignored design unit "display" at part2.v(104) due to previous errors File: D:/傈傍/3切斥1切扁/叼瘤判角氰/Quartus/角嚼12/2/part2.v Line: 104
Info: Found 0 design units, including 0 entities, in source file part2.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
    Info: Allocated 142 megabytes of memory during processing
    Error: Processing ended: Sat May 26 19:25:11 2007
    Error: Elapsed time: 00:00:01