cameradriver.v

This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:25:19 03/15/2007 
// Design Name: 
// Module Name:   CameraDriver 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

`include "async_receiver.v"
`include "async_transmitter.v"
`include "HexDisplay.v"

module CameraDriver(CLK,TX,RX,OE,WE,Addr,AN,SEG, RESET,DATA,PCLK,Vref,Href,Y);

	input 					CLK,RX,PCLK,Vref,Href;
	input		[7:0]			Y;
	
	output					OE,WE,TX,RESET;
	output 	[3:0]			AN;
	output	[6:0]			SEG;
	output	[17:0]		Addr;	//76800
	
	inout	  	[7:0]			DATA;
	
	reg		[7:0]			Hcount, pixeldata;
	
	reg						transmit,readwrite,OE,WE,oldPCLK, oldVref, RESET;
	reg		[3:0]			state = 4'b0000;
	reg		[7:0]			sndval,rcdval;
	reg		[17:0]		AddrEnd,Addr;
	reg		[31:0]		counter;
	
	wire						BUSY,rdysrt;
	wire		[7:0]			rdata;
	
	parameter WAIT_HANDSHAKE = 4'b0000;		//State 0
	parameter INIT_WRITE 	 = 4'b0001;		//State 1
	parameter WAIT_VSYNC		 = 4'b0010;		//State 2
	parameter WRITE_PIXEL 	 = 4'b0011;		//State 3
	parameter INIT_READ 		 = 4'b0100;		//State 4
	parameter READ_PIXEL 	 = 4'b0101;		//State 5
	parameter CHECK_READ 	 = 4'b0110;		//State 6
	parameter RESET_WE		 = 4'b0111;		//State 7
	parameter DELAY			 = 4'b1000;		//state 8
	parameter WHITE			 = 8'b01010111;
	parameter BLACK			 = 8'b01000010;

	async_receiver ar(
		.clk(CLK), 
		.RxD(RX), 
		.RxD_data_ready(rdysrt),
		.RxD_data(rdata)
		//.RxD_endofpacket,
		//.RxD_idle
		);

	async_transmitter at(
		.clk(CLK), 
		.TxD_start(transmit), 
		.TxD_data(rcdval), 
		.TxD(TX),
		.TxD_busy(BUSY)
		);


	HexDisplay dis(rdata,CLK,AN,SEG);

	assign DATA = readwrite ? 8'bz : Y; 
	
	always @ (posedge CLK)
		begin
		
			casex(state)
					WAIT_HANDSHAKE:	//State 0
						begin
							sndval <= rdata;
							RESET <= 1;
							if(rdysrt == 1 && rdata == 3)	
									state <= INIT_WRITE;
								else
									state <= WAIT_HANDSHAKE;        
						end
					INIT_WRITE:	//State 1
						begin
							OE <= 1;
							WE <= 1;
							Addr <= 0;
							transmit <= 0;
							RESET <= 0;
							state <= WAIT_VSYNC;
							oldPCLK <= 0;
						
							Hcount <= 0;	//Sets the Href Count to 0
						end
					WAIT_VSYNC:		//State 2
						begin
							if(!Vref && oldVref)
								state <= WRITE_PIXEL;
								
							oldVref <= Vref;
						end
					WRITE_PIXEL:	//State 3
						begin
							if(PCLK && !oldPCLK && Href)
								begin
									readwrite <= 0;
									OE <= 1;
									WE <= 0;
									Addr <= Addr + 1;
									pixeldata <= WHITE;
									Hcount <= Hcount + 1;
								end
								
							else
								begin
									WE <= 0;
									readwrite <= 1;
									//Addr <= Addr + 1;
									pixeldata <= BLACK;
								end
								
							oldPCLK <= PCLK;
							
							if(Vref == 1) 
								begin
									state   <= INIT_READ;
					//				state <= DELAY;
									counter <= 0;
									AddrEnd <= Addr;
								end
							else state <= WRITE_PIXEL;			
							
						end
							
					INIT_READ:	//State 4
						begin
							Addr  <= 0;
							OE    <= 1;
							WE    <= 1;
							state <= READ_PIXEL;						
						end
					READ_PIXEL:	//State 5
						begin
															
							if(!BUSY)
								begin
									readwrite <= 1;
									OE <= 0;
									WE <= 1;
									transmit <= 1;
									state <= CHECK_READ;
									rcdval <= DATA;
									Addr <= Addr + 1;
								end
							else
								begin
									state <= READ_PIXEL;
									transmit <= 0;
								end
						end
					CHECK_READ:	//State 6
						begin
							if(Addr >= AddrEnd) state <= INIT_WRITE;
							else state <= READ_PIXEL;						
							
							OE <= 1;
							transmit <= 0;	
						end
					RESET_WE:
						begin
							WE <= 1;
							state <= WRITE_PIXEL;	
						end

					DELAY:
						begin
							if(counter == 50000000)
								state <= INIT_READ;
							
							else
								begin
									counter <= counter + 1;
									state <= DELAY;
								end
							end
			endcase
		end
endmodule