libsi3000init.c

来自「Audio compression on embedded board」· C语言 代码 · 共 560 行 · 第 1/2 页

/*-----------------------------------------------------------------------------
      Cofiguration of DCI peripheral for setting up SI 3000 codec Registers.
-----------------------------------------------------------------------------*/
    DCICON1 = 0x0000;      		       //Ensure DCI module is placed in known
    DCICON2 = 0x0000;                   //state.
    DCICON3 = 0x0000;
    TSCON   = 0x0000;
    RSCON   = 0x0000;
    _TRISF6 = 0x01;       			   //Make codec reset switch port pin as 
                                       //inputfor now.Ensure port pins are 
                         			   //setcorrectly (Not really required 
                         		       //since DCI takes control of it's pins)

    //TRISG = 0x5000;		 		   //CSDI pin configured for input
    TRISG = 0xD000;	    			   //COFS output to Si3000 in DCI Master 
			   			 			   //mode CSCK output to Si3000

    DCICON1 = 0x0040;	 			   //Set for multichannel frame sync mode
						 			   //Data tx/rx begins 1clock after Fs pulse
						 			   //Data changes on rising, sampled on falling
						 			   //Tristate output CSDO pin when not txing
						 			   //Frame sync generated by dsPIC DCI
						 			   //Clock is output from DCI
						 			   //Ensure module is disabled for now

    DCICON2 = 0x04EF;				   //Data word size is 16-bits (bits 3:0)
									   //Data frame is 8 words (bits 8:5)
									   //Set buffer length control (2 data words
									   //Will be buffered between interrupts)


    DCICON3 = 0x0000;       			   //Initialize DCI bit clock generator

   
    _COFSD = 0x01;
    _CSCKD = 0x01;

    RSCON = 0x0001;				       //Set receive slot 1 enable RSCON

    TSCON = 0x0001;				       //Set transmit slot 1 enable TSCON

    _DCIIF = 0x00;      			       //Ensure DCI interrupt flag is reset IFS2


    _DCIIE = 0x00;	    			   //ISR processing is disabled for now IEC2





    _LATF1 = 0x01;
    _LATF2 = 0x01;
    _TRISF1 = 0x00;
    _TRISF2 = 0x00;




/*-----------------------------------------------------------------------------
            Setup of SI 3000 codec through DCI peripheral on dsPIC30F device.
-----------------------------------------------------------------------------*/
    TXBUF0 = PLUS_ONE_WITH_SECONDARY;   //Load TXBUF0 with a value that
                                       //requests a secondary frame

    TXBUF1 = (WRITE_PLL1_DIVIDE_N1|g711.pLL1divideN1); 
                          				
                                       //Load TXBUF1 with a value that will 
                            		   //initiate a WRITE to PLL Divide Control
                                       //Register 3 in the Si3000.


    _LATF1 = 0x00;
    _LATF2 = 0x00;
    _TRISF1 = 0x00;
    _TRISF2 = 0x00;
    asm("REPEAT #200");
    asm("nop");

   _LATF1 = 0x01;
   _LATF2 = 0x01;

   _RF6 = 0x00;						   //Synchronize DCI with Si3000to
                                       //ensure first frame synce is
                                       //aligned with TXBUF0.
                                       //This is not really required
                                       //when the DCI is Master and
                                       //Codec is the Slave but is
                                       //required when the Codecis the
                                       //Master and DCI is the Slave.
   asm("nop");
   _TRISF6 = 0x00;		               //Reset codec
   asm("repeat  #40");                 //Transmit a minimum pulse
   asm("nop");                         //width of 5uS

   _TRISF6 = 0x01;					   //Release codec

   _DCIEN = 0x1;			    	   //Enable DCI module
									   //This ensures the first primary
                                       //and secondary frame use data
                                       //loaded already into TXBUF0
                                       //and TXBUF1

//-------------------------------------------------------



   while ( ! _TMPTY );				   //Wait until TXBUF0 and TXBUF1
       							       //have been movedto their shadow
									   //registers for transmission

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;   //Load TXBUF0 with a value that
       						           //requests a secondary frame

   TXBUF1 = (WRITE_PLL1_MULTIPLY_M1 | g711.pLL1multiplyM1);
                          							        
                                       //Load TXBUF1 with avalue that will ini-
                            		   //tiate aWRITE to PLL Multiply Register4
							            
   while( ! _TMPTY );                  //Wait until TXBUF0 and TXBUF1
                                	   //have been moved to their shadow
                                       //registers for transmission

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;   //Load TXBUF0 with a value that
       							       //requests a secondary frame

   TXBUF1 = (WRITE_CONTROL_1  | g711.control1);
                                       //Load TXBUF1 with a value that
                            		   //will power up/down line driver
                               		   //and the speaker driver in Si3000
                             		   //Control Register 1

   while ( ! _TMPTY ); 				   //Wait until TXBUF0 and TXBUF1
                      				   //have been moved to their shadow
                                       //registers for transmission

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;   //Load TXBUF0 with a value that
                           			   //requests a secondary frame

   TXBUF1 = (WRITE_CONTROL_2 | g711.control2); //Load TXBUF1 with a value that
                          				//will initialize Control2
                                        //Register 2.
   while ( ! _TMPTY );

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;	//Load TXBUF0 with a value that
                           				//requests a secondary frame

   TXBUF1 = (WRITE_RX_GAIN_CONTROL_1 | g711.rxgaincontroL1);//Load TXBUF1 with
                          				//a value that will initialize
                                        //RX Gain Control1 Register.


   while ( ! _TMPTY);					//Wait until TXBUF0 and TXBUF1
                         				//have been moved to their shadow
                                        //registers for transmission

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;    //Load TXBUF0 with a value that
                                        //requests a secondary frame

   TXBUF1 = (WRITE_ADC_VOLUME_CONTROL  | g711.adcvolumecontrol);//Load TXBUF1
                            			//with a value that will
                                        //initialize ADC volume contol
                                        //Register6.
   while ( ! _TMPTY );					//Wait until TXBUF0 and TXBUF1
                         				//have been moved to their shadow
                                        //registers for transmission

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;    //Load TXBUF0 with a value that
                     					//requests a secondary frame

   TXBUF1 = (WRITE_DAC_VOLUME_CONTROL |g711.dacvolumecontrol);//Load TXBUF1
                           				// with a value that that will
                                        //initialize DAC Volume Control 
                                        // Register7   

   while ( ! _TMPTY );					//Wait until TXBUF0 and TXBUF1
                          			    //have been moved to their shadow
                                        //registers for transmission

   TXBUF0 = PLUS_ONE_WITH_SECONDARY;    //Load TXBUF0 with a value that
                      					//requests a secondary frame
   TXBUF1 = (WRITE_ANALOG_ATTENUATION | g711.analogattenuation);//Load TXBUF1
                           				//with a value that that
                                        //will initialize Analog
                                        //attenuation Control Register9.
   while(!_TMPTY);						//Wait until TXBUF0 and TXBUF1
                          				//have been moved to their shadow
                                        //registers for transmission

/*-----------------------------------------------------------------------------
Note that the TMPTY bit only gives a status of whether or not TXBUF registers
are ready to accept data. This does not tell you if the transmissions themselves
were completed.So, we need to test the SLOT<3:0> bits in the DCISTAT register.
While testing we will ensure that TXBUF0 and TXBUF1 shadow registers have been
fully transmitted on TimeSlot0 two times each. This will guarantee that
initialization of the codec is complete
-----------------------------------------------------------------------------*/
   temp1 = 0x0f00;						//Set up a mask for the SLOT bits
   do
   {									//Read the DCISTAT register
     temp2 = DCISTAT;					//Logical-AND to extract SLOT bits
     temp2 &= temp1;
   } while ( temp2 ); 					//Wait until SLOT bits reach 0b0000
 								        //Did TXBUF0 get transmitted?

	 do
   {									//Read the DCISTAT register
     temp2 = DCISTAT;					//Logical-AND to extract SLOT bits
     temp2 &= temp1;
   } while ( ! temp2 );					//Wait until SLOT bits reach non-zero
          								//Did TXBUF1 get transmitted?

	 do
   {									//Read the DCISTAT register
     temp2 = DCISTAT;					//Logical-AND to extract SLOT bits
     temp2 &= temp1;
   } while ( temp2 ); 					//Wait until SLOT bits reach 0b0000
          								//Did TXBUF0 get transmitted?

	 do
   {									//Read the DCISTAT register
     temp2= DCISTAT;					//Logical-AND to extract SLOT bits
     temp2 &= temp1;
   } while ( ! temp2 );					//Wait until SLOT bits reach 0b0000
        								//Did TXBUF0 get transmitted?

	 while ( ! _ROV );					//Testing overflow bit

   temp1 = RXBUF0;						//Dummy reads to clear
   temp1 = RXBUF1;						//overflow conditions

	 _DCIEN = 0x00;						//Disable the DCI module

/*-----------------------------------------------------------------------------
Now re-initialize some aspects of the DCI communication for normal interrupt
driven operation based on user settings done in dci and codecsetup structures.
-----------------------------------------------------------------------------*/

   DCICON1 = DCICON1VAL;    		    //Set mode.
										//Data txmit/rx setup.
										//Data change setup.
              							//Tristate/set low output CSDO pin when
                                        //not txing.
										//Frame sync generated by dsPIC DCI/SI 3000.
										//Clock is output from DCI/SI 3000.
										//Ensure module is disabled for now
   DCICON2 = DCICON2VAL;			    //Set Data word size .(bits 3:0)
										//Set data frame size.(bits 8:5)
   // DCICON3 = g711.bcg1;                //Set DCI bit clock generator.
   DCICON3 = 0x0000;
   _COFSD = 0x01;
   _CSCKD = 0x01; 
   RSCON = RSCONVAL;                    //Set receive slot enable bits.
   TSCON = TSCONVAL;                    //Set transmit slot enable bits.
   codecdata.countFill = 0x0000;        //Clear counter that keeps track of data
                                        //filled into ping pong buffers.
   codecdata.countLoad = 0x0000;        //Clear counter that keeps track of data
                                        //retrieved from ping pong buffers.

   codecdata.fBlockdone = 0x00;			//Clear flag that indicates whether or
 										//not one sample ping pong buffer
                                        //has been filled.
   _DCIEN = 0x01;
   

	  
   temp1 = 0x0100;
   do
   {
     temp2 = 0xFFFF;

     while(--temp2);
 
   } while(--temp1);
  }
}
/*-----------------------------------------------------------------------------
                      END OF FILE:  libSi3000Init.c
-----------------------------------------------------------------------------*/