📄 libsi3000init.c
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TSCON = 0x0000;
RSCON = 0x0000;
_TRISF6 = 0x01; //general pin direction independent of
//Master/Slave mode
_TRISG13 = 0x00; //make codec reset switch "OR" node ani/p.
_TRISG12 = 0x01;
_RSE0 = 0x01; //Set receive slot 0 enable RSCON
_TSE0 = 0x01; //Set transmit slot 0 enable TSCON
DCICON1 = 0x0060; //Frame sync mode (bits 1:0)
//set for multichannel frame sync mode
//data justification control
//data tx/rx begins with Fs pulse
//sample clock edge control bit
//data changes on rising, sampled on
//falling
/******************************************************************************
Si3000 is Master Controller / DCI Slave (Errata workaround)
******************************************************************************/
_TRISG15 = 0x01; //ensure port pins are set correctly
//COFS input driven by Si3000
_TRISG14 = 0x01; //CSCK input driven by Si3000
DCICON2 = 0x0CEF; //data word size is 16-bits (bits 3:0)
//data frame is 8 words (bits 8:5)
//set buffer length control (4 data words
//will be buffered between interrupts)
//4 words buffered per interrupt
DCICON3 = 0x0000; //ensure bit clock count = 0
_COFSD = 0x01; //frame sync direction control
//frame sync driven by Si3000
_CSCKD = 0x01; //clock is input from Si3000
//clock is input to DCI from Si3000
_RSE1 = 0x01; //receive slot enable enable time slot 1
_TSE1 = 0x01; //transmit slot enable
//enable time slot1(for errata)
_DCIEN = 0x00; //disable DCI module
/******************************************************************************
Subroutine: Initialization of Si3000 Codec
******************************************************************************/
_LATF1 = 0x01; //set Si3000 reset pin high
_LATF2 = 0x01;
_TRISF1 = 0x00; //set pin as output
_TRISF2 = 0x00;
/******************************************************************************
DCI Module Errata workaround
Using all 4 TXBUF registers to reduce interrupt frequency
******************************************************************************/
//WRITE to PLL1_Divide_N1 Control Register 3
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_PLL1_DIVIDE_N1>>1)|((g711.pLL1divideN1)>>1);
//Load TXBUF1 with a
//value that will initiate a
//WRITE to PLL Divide Control
//Register 3 in the Si3000.
TXBUF3 = 0x0000; //Load extra write for LSb of
//secondary frame
//synchronize DCI with Si3000 to ensure first frame synce is aligned with TXBUF0
_LATF1 = 0x00; //set Si3000 reset pin low
_LATF2 = 0x00;
_TRISF1 = 0x00; //ensure pin is output
_TRISF2 = 0x00;
asm("REPEAT #200");
asm("nop"); //minimum pulse of 5uS
_LATF1 = 0x01; //release codec
_LATF2 = 0x01;
asm("nop");
_RF6 = 0x00; //Synchronize DCI with Si3000to
//ensure first frame synce is
//aligned with TXBUF0.
//This is not really required
//when the DCI is Master and
//Codec is the Slave but is
//required when the Codecis the
//Master and DCI is the Slave.
asm("nop");
_TRISF6 = 0x00; //Reset codec
asm("repeat #40"); //Transmit a minimum pulse
asm("nop"); //width of 5uS
_TRISF6 = 0x01; //Release codec
_DCIEN = 0x01; //enable DCI module
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to PLL1_Divide_M1 Control Register 4
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_PLL1_MULTIPLY_M1>>1)|((g711.pLL1multiplyM1)>>1);
//Load TXBUF1 with a
//value that will initiate a
//WRITE to PLL Multiply
//Register 4
TXBUF3 = 0x8000; //Load extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to RX Gain Control 1 Register 5
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_RX_GAIN_CONTROL_1>>1)|((g711.rxgaincontroL1)>>1);
//Load TXBUF1 with
//a value that will initialize
//RX Gain Control1 Register.
TXBUF3 = 0x0000; //extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to ADC Volume Control Register 6
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_ADC_VOLUME_CONTROL>>1)|((g711.adcvolumecontrol)>>1);
//Load TXBUF1
//with a value that will
//initialize ADC volume contol
//Register6.
TXBUF3 = 0x0000; //Load extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to DAC Volume Control Register 7
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_DAC_VOLUME_CONTROL>>1)|((g711.dacvolumecontrol)>>1);
//Load TXBUF1 with
//a value that that will
//initialize DAC Volume Control
//Register 7
TXBUF3 = 0x8000; //Load extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to Analog Attenuation Register 8
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_ANALOG_ATTENUATION>>1)|((g711.analogattenuation)>>1);
//Load TXBUF1
//with a value that that
//will initialize Analog
//attenuation Control Register9
TXBUF3 = 0x0000; //Load extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to Control Register 1
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_CONTROL_1>>1)|((g711.control1)>>1);
//Load TXBUF1 with a value that
//will initialize Control1
//Register 1.
TXBUF3 = 0x0000; //Load extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//at this point we are ready to load the TXBUF registers again
//WRITE to Control Register 2
TXBUF0 = PLUS_ONE_WITH_SECONDARY >> 1; //Load TXBUF0 with a value that
//requests a secondary frame
TXBUF1 = 0x8000; //Load extra write for setting MSbit
//of TS1 (LSbit of TS0)
TXBUF2 = (WRITE_CONTROL_2>>1)|((g711.control2)>>1);
//Load TXBUF1 with a value that
//will initialize Control2
//Register 2.
TXBUF3 = 0x0000; //Load extra write for LSb of
//secondary frame
while ( ! _TMPTY );
/*---------------------------------------------------------------------------*/
//simple check for testing overflow bit functionality
while ( ! _ROV ); //Testing overflow bit
temp1 = RXBUF0; //Dummy reads to clear
temp1 = RXBUF1; //overflow conditions
temp1 = RXBUF2; //prepare for reads
temp1 = RXBUF3;
_DCIEN = 0x00; //disable DCI module
/******************************************************************************
Delay to allow calibration to occur
******************************************************************************/
DCICON1 = 0x0060; //Frame sync mode (bits 1:0)
//set for multichannel frame sync mode
//data justification control
//data tx/rx begins with Fs pulse
//sample clock edge control bit
//data changes on rising, sampled on falling
DCICON2 = 0x0DEF; //Set Data word size 16-bits .(bits 3:0)
//Set data frame size 16 - words.(bits 8:5)
DCICON3 = 0x0000; //set buffer length control (4 data words
//will be buffered between interrupts)
//4 words buffered per interrupt
//ensure bit clock count = 0
_COFSD = 0x01; //frame sync direction control
//frame sync driven by Si3000
_CSCKD = 0x01; //clock is input from Si3000
//clock is input to DCI from Si3000
_DCIEN = 0X01;
temp1 = 0x0100;
do
{
temp2 = 0xFFFF;
while(--temp2);
}while(--temp1);
}
}
/*-----------------------------------------------------------------------------
END OF FILE: libSi3000Init.c
-----------------------------------------------------------------------------*/
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