syslib.c

ARM板驱动程序源代码

char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


/* locals */


/* defines */


/* externals */

IMPORT int  at91IntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);


/* globals */


/* forward LOCAL functions declarations */


/* forward declarations */

char *	sysPhysMemTop (void);


#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif

/* included source files */

#ifdef INCLUDE_FLASH



#include "mem/nvRamToFlash.c"
#include "flashMem.c"
#else 
#include "mem/nullNvRam.c"
#endif
#include "vme/nullVme.c"
#include "sysSerial.c"

#include "timer/at91Timer.c"
#include "sio/at91Sio.c"
#include "intrCtl/at91Intr.c"

/*
#include "pciIomapLib.c"
#include "pciIomapShow.c"
#include "sysEnd.c"
*/
#ifdef INCLUDE_WINDML
//#include "ambaKbd.c"
//#include "ambaMse.c"
//#include "sysWindML.c"
#endif /* INCLUDE_WINDML */

#include "end/at91eth.c"

#ifdef INCLUDE_MMC
#include "mmc/mmcDev.c"
#endif

#ifdef INCLUDE_SPI_DATAFLASH_CARD
#include "dataflash/dataflashdev.c"
#endif

#ifdef INCLUDE_DISPLAY
#include "display/at91display.c"
#endif

#ifdef INCLUDE_USB_SLAVE_BULK
#include "usbslave/at91UsbSlave.c"
#endif

#ifdef INCLUDE_SOUND_CODEC
#include "audio/dac3550drv.c"
#endif


#ifdef INCLUDE_PCMCIA
#include "cf/pccardLib.c"
#endif
/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char *sysModel (void)
    {
#if	defined(CPU_7TDMI)
    return	"ARM Integrator - ARM7TDMI (ARM)";
#elif	defined(CPU_7TDMI_T)
    return	"ARM Integrator - ARM7TDMI (Thumb)";
#elif	defined(CPU_720T)
    return	"ARM Integrator - ARM720T (ARM)";
#elif	defined(CPU_720T_T)
    return	"ARM Integrator - ARM720T (Thumb)";
#elif	defined(CPU_740T)
    return	"ARM Integrator - ARM740T (ARM)";
#elif	defined(CPU_740T_T)
    return	"ARM Integrator - ARM740T (Thumb)";
#elif	defined(CPU_920T)
    return	"ARM Integrator - ARM920T (ARM)";
#elif	defined(CPU_920T_T)
    return	"ARM Integrator - ARM920T (Thumb)";
#elif	defined(CPU_940T)
    return	"ARM Integrator - ARM940T (ARM)";
#elif	defined(CPU_940T_T)
    return	"ARM Integrator - ARM940T (Thumb)";
#elif   defined(CPU_946ES)
    return      "ARM Integrator - ARM946ES (ARM)";
#elif   defined(CPU_946ES_T)
    return      "ARM Integrator - ARM946ES (Thumb)";
#elif   defined(CPU_966ES)
    return      "ARM Integrator - ARM966ES (ARM)";
#elif   defined(CPU_966ES_T)
    return      "ARM Integrator - ARM966ES (Thumb)";
#else
#error CPU not supported
#endif	/* defined(CPU_7TDMI) */
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T)
/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/

void sysHwInit0 (void)
    {

#ifdef INCLUDE_CACHE_SUPPORT
    /*
     * Install the appropriate cache library, no address translation
     * routines are required for this BSP, as the default memory map has
     * virtual and physical addresses the same.
     */

#if	defined(CPU_720T) || defined(CPU_720T_T)
    cacheArm720tLibInstall (NULL, NULL);
#elif   defined(CPU_740T) || defined(CPU_740T_T)
    cacheArm740tLibInstall (NULL, NULL);
#elif   defined(CPU_920T) || defined(CPU_920T_T)
    cacheArm920tLibInstall (NULL, NULL);
#elif   defined(CPU_940T) || defined(CPU_940T_T)
    cacheArm940tLibInstall (NULL, NULL);
#elif   defined(CPU_946ES) || defined(CPU_946ES_T)
    cacheArm946eLibInstall (NULL, NULL);
#endif
#endif /* INCLUDE_CACHE_SUPPORT */


#if defined(INCLUDE_MMU)
    /* Install the appropriate MMU library and translation routines */

#if	defined(CPU_720T) || defined(CPU_720T_T)
    mmuArm720tLibInstall (NULL, NULL);
#elif   defined(CPU_740T) || defined(CPU_740T_T)
    mmuArm740tLibInstall (NULL, NULL);
#elif   defined(CPU_920T) || defined(CPU_920T_T)
    mmuArm920tLibInstall (NULL, NULL);
#elif   defined(CPU_940T) || defined(CPU_940T_T)
    mmuArm940tLibInstall (NULL, NULL);
#elif   defined(CPU_946ES) || defined(CPU_946ES_T)
    mmuArm946eLibInstall (NULL, NULL);
#endif

#endif /* defined(INCLUDE_MMU) */

    return;
    }
#endif /* defined(720T/740T/920T/940T/946ES) */

#if defined(INCLUDE_PCI)
/*******************************************************************************
*
* sysV3Init - initialise the V3 PCI bridge controller
*
* This function initialises the V3 chip which controls the PCI bridge.
*
* RETURNS: N/A
*/

void sysV3Init (void)
    {
    volatile int i, j;

    /* setting this register will take the V3 out of reset */

    *(UINT32 *)(INTEGRATOR_SC_PCIENABLE) = 1;


    /* wait a few usecs to settle the device and the PCI bus (no timers yet) */

    for (i = 0; i < 100 ; i++)
	   j = i + 1;

    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */

    *(UINT16 *)(V3_BASE + V3_LB_IO_BASE) = (UINT16)(V3_BASE >> 16);

    do
	{
        *(UINT8 *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
	*(UINT8 *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
	}
    while (*(UINT8 *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
	    *(UINT8 *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);

    /* Make sure that V3 register access is not locked, if it is, unlock it */

    if ((*(UINT16 *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK) ==
							    V3_SYSTEM_M_LOCK)
	*(UINT16 *)(V3_BASE + V3_SYSTEM) = 0xA05F;

    /*
     * Ensure that the slave accesses from PCI are disabled while we
     * setup windows
     */

    *(UINT16 *)(V3_BASE + V3_PCI_CMD) &=
    				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);


    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */

    *(UINT16 *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;

    /* Make all accesses from PCI space retry until we're ready for them */

    *(UINT16 *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;

    /*
     * Set up any V3 PCI Configuration Registers that we absolutely have to
     * LB_CFG controls Local Bus protocol.
     * Enable LocalBus byte strobes for READ accesses too.
     * set bit 7 BE_IMODE and bit 6 BE_OMODE
     */

    *(UINT16 *)(V3_BASE + V3_LB_CFG) |= 0x0C0;

    /*
     * PCI_CMD controls overall PCI operation.
     * Enable PCI bus master.
     */

    *(UINT16 *)(V3_BASE + V3_PCI_CMD) |= 0x04;

    /*
     * PCI_MAP0 controls where the PCI to CPU memory window is on the Local Bus
     */

    *(UINT32 *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
					(V3_PCI_MAP_M_ADR_SIZE_512M |
					V3_PCI_MAP_M_REG_EN |
					V3_PCI_MAP_M_ENABLE);

    /* PCI_BASE0 is the PCI address of the start of the window */

    *(UINT32 *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;

    /* PCI_MAP1 is LOCAL address of the start of the window */

    *(UINT32 *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
			 V3_PCI_MAP_M_ENABLE);

    /* PCI_BASE1 is the PCI address of the start of the window */

    *(UINT32 *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;

    /*
     * Set up the windows from local bus memory into PCI configuration,
     * I/O and Memory.
     * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
     */

    *(UINT16 *)(V3_BASE +V3_LB_BASE2) =
    			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
    *(UINT16 *)(V3_BASE + V3_LB_MAP2) = 0;

    /*
     * PCI Configuration, use LB_BASE1/LB_MAP1.
     *
     * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
     * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
     * (INTEGRATOR_PCI_BASE == PCI_MEM_BASE)
     */

    *(UINT32 *)(V3_BASE + V3_LB_BASE0) =
    			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);

    *(UINT16 *)(V3_BASE + V3_LB_MAP0) =
    				((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;

    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */

    *(UINT32 *)(V3_BASE + V3_LB_BASE1) =
    			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);

    *(UINT16 *)(V3_BASE + V3_LB_MAP1) =
    			(((INTEGRATOR_PCI_BASE + SZ_256M) >> 20) << 4) | 0x0006;

    /*
     * Allow accesses to PCI Configuration space
     * and set up A1, A0 for type 1 config cycles
     */

    *(UINT16 *)(V3_BASE + V3_PCI_CFG) = ((*(UINT16 *)(V3_BASE + V3_PCI_CFG)) &
			   ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
			   V3_PCI_CFG_M_AD_LOW0;

    /* now we can allow in PCI MEMORY accesses */

    *(UINT16 *)(V3_BASE + V3_PCI_CMD) =
		    (*(UINT16 *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;

    /*
     * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
     * initialise and lock the V3 system register so that no one else
     * can play with it
     */

   *(UINT16 *)(V3_BASE + V3_SYSTEM) =
		    (*(UINT16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;

   *(UINT16 *)(V3_BASE + V3_SYSTEM) =
   			(*(UINT16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;

    return;
    }
#endif /* defined(INCLUDE_PCI) */

/*******************************************************************************
*
* sysHwInit - initialize the CPU board hardware
*
* This routine initializes various features of the hardware.
* Normally, it is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    /* install the IRQ/SVC interrupt stack splitting routine */

    _func_armIntStackSplit = sysIntStackSplit;