at91rm9200_sys.h

ARM板驱动程序源代码

#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) /* (MC) Area size 1KByte*/
#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) /* (MC) Area size 2KByte*/
#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) /* (MC) Area size 4KByte*/
#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) /* (MC) Area size 8KByte*/
#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) /* (MC) Area size 16KByte*/
#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) /* (MC) Area size 32KByte*/
#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) /* (MC) Area size 64KByte*/
#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) /* (MC) Area size 128KByte*/
#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) /* (MC) Area size 256KByte*/
#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) /* (MC) Area size 512KByte*/
#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) /* (MC) Area size 1MByte*/
#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) /* (MC) Area size 2MByte*/
#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) /* (MC) Area size 4MByte*/
#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) /* (MC) Area size 8MByte*/
#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) /* (MC) Area size 16MByte*/
#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) /* (MC) Area size 64MByte*/
#define AT91C_MC_BA           (0x3FFFF << 10) /* (MC) Internal Area Base Address*/
/* -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------*/
/* -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------*/
#define AT91C_MC_PUEB         (0x1 <<  0) /* (MC) Protection Unit enable Bit*/


/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface*/
/* ******************************************************************************/
/* -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------*/
#define AT91C_RTC_UPDTIM      (0x1 <<  0) /* (RTC) Update Request Time Register*/
#define AT91C_RTC_UPDCAL      (0x1 <<  1) /* (RTC) Update Request Calendar Register*/
#define AT91C_RTC_TIMEVSEL    (0x3 <<  8) /* (RTC) Time Event Selection*/
#define 	AT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) /* (RTC) Minute change.*/
#define 	AT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) /* (RTC) Hour change.*/
#define 	AT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) /* (RTC) Every day at midnight.*/
#define 	AT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) /* (RTC) Every day at noon.*/
#define AT91C_RTC_CALEVSEL    (0x3 << 16) /* (RTC) Calendar Event Selection*/
#define 	AT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) /* (RTC) Week change (every Monday at time 00:00:00).*/
#define 	AT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) /* (RTC) Month change (every 01 of each month at time 00:00:00).*/
#define 	AT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) /* (RTC) Year change (every January 1 at time 00:00:00).*/
/* -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------*/
#define AT91C_RTC_HRMOD       (0x1 <<  0) /* (RTC) 12-24 hour Mode*/
/* -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------*/
#define AT91C_RTC_SEC         (0x7F <<  0) /* (RTC) Current Second*/
#define AT91C_RTC_MIN         (0x7F <<  8) /* (RTC) Current Minute*/
#define AT91C_RTC_HOUR        (0x3F << 16) /* (RTC) Current Hour*/
#define AT91C_RTC_AMPM        (0x1 << 22) /* (RTC) Ante Meridiem, Post Meridiem Indicator*/
/* -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------*/
#define AT91C_RTC_CENT        (0x3F <<  0) /* (RTC) Current Century*/
#define AT91C_RTC_YEAR        (0xFF <<  8) /* (RTC) Current Year*/
#define AT91C_RTC_MONTH       (0x1F << 16) /* (RTC) Current Month*/
#define AT91C_RTC_DAY         (0x7 << 21) /* (RTC) Current Day*/
#define AT91C_RTC_DATE        (0x3F << 24) /* (RTC) Current Date*/
/* -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register --------*/
#define AT91C_RTC_SECEN       (0x1 <<  7) /* (RTC) Second Alarm Enable*/
#define AT91C_RTC_MINEN       (0x1 << 15) /* (RTC) Minute Alarm*/
#define AT91C_RTC_HOUREN      (0x1 << 23) /* (RTC) Current Hour*/
/* -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------*/
#define AT91C_RTC_MONTHEN     (0x1 << 23) /* (RTC) Month Alarm Enable*/
#define AT91C_RTC_DATEEN      (0x1 << 31) /* (RTC) Date Alarm Enable*/
/* -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------*/
#define AT91C_RTC_ACKUPD      (0x1 <<  0) /* (RTC) Acknowledge for Update*/
#define AT91C_RTC_ALARM       (0x1 <<  1) /* (RTC) Alarm Flag*/
#define AT91C_RTC_SECEV       (0x1 <<  2) /* (RTC) Second Event*/
#define AT91C_RTC_TIMEV       (0x1 <<  3) /* (RTC) Time Event*/
#define AT91C_RTC_CALEV       (0x1 <<  4) /* (RTC) Calendar event*/
/* -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register --------*/
/* -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------*/
/* -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------*/
/* -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------*/
/* -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------*/
#define AT91C_RTC_NVTIM       (0x1 <<  0) /* (RTC) Non valid Time*/
#define AT91C_RTC_NVCAL       (0x1 <<  1) /* (RTC) Non valid Calendar*/
#define AT91C_RTC_NVTIMALR    (0x1 <<  2) /* (RTC) Non valid time Alarm*/
#define AT91C_RTC_NVCALALR    (0x1 <<  3) /* (RTC) Nonvalid Calendar Alarm*/


/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR System Timer Interface*/
/* ******************************************************************************/
/* -------- ST_CR : (ST Offset: 0x0) System Timer Control Register --------*/
#define AT91C_ST_WDRST        (0x1 <<  0) /* (ST) Watchdog Timer Restart*/
/* -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register --------*/
#define AT91C_ST_PIV          (0xFFFF <<  0) /* (ST) Watchdog Timer Restart*/
/* -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register --------*/
#define AT91C_ST_WDV          (0xFFFF <<  0) /* (ST) Watchdog Timer Restart*/
#define AT91C_ST_RSTEN        (0x1 << 16) /* (ST) Reset Enable*/
#define AT91C_ST_EXTEN        (0x1 << 17) /* (ST) External Signal Assertion Enable*/
/* -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register --------*/
#define AT91C_ST_RTPRES       (0xFFFF <<  0) /* (ST) Real-time Timer Prescaler Value*/
/* -------- ST_SR : (ST Offset: 0x10) System Timer Status Register --------*/
#define AT91C_ST_PITS         (0x1 <<  0) /* (ST) Period Interval Timer Interrupt*/
#define AT91C_ST_WDOVF        (0x1 <<  1) /* (ST) Watchdog Overflow*/
#define AT91C_ST_RTTINC       (0x1 <<  2) /* (ST) Real-time Timer Increment*/
#define AT91C_ST_ALMS         (0x1 <<  3) /* (ST) Alarm Status*/
/* -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register --------*/
/* -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register --------*/
/* -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register --------*/
/* -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register --------*/
#define AT91C_ST_ALMV         (0xFFFFF <<  0) /* (ST) Alarm Value Value*/
/* -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register --------*/
#define AT91C_ST_CRTV         (0xFFFFF <<  0) /* (ST) Current Real-time Value*/


/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Power Management Controler*/
/* ******************************************************************************/
/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
#define AT91C_PMC_PCK         (0x1 <<  0) /* (PMC) Processor Clock*/
#define AT91C_PMC_UDP         (0x1 <<  1) /* (PMC) USB Device Port Clock*/
#define AT91C_PMC_MCKUDP      (0x1 <<  2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend*/
#define AT91C_PMC_UHP         (0x1 <<  4) /* (PMC) USB Host Port Clock*/
#define AT91C_PMC_PCK0        (0x1 <<  8) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK1        (0x1 <<  9) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK2        (0x1 << 10) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK3        (0x1 << 11) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK4        (0x1 << 12) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK5        (0x1 << 13) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK6        (0x1 << 14) /* (PMC) Programmable Clock Output*/
#define AT91C_PMC_PCK7        (0x1 << 15) /* (PMC) Programmable Clock Output*/
/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------*/
/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------*/
/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
#define AT91C_PMC_CSS         (0x3 <<  0) /* (PMC) Programmable Clock Selection*/
#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) /* (PMC) Slow Clock is selected*/
#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) /* (PMC) Main Clock is selected*/
#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) /* (PMC) Clock from PLL A is selected*/
#define 	AT91C_PMC_CSS_PLLB_CLK             (0x3) /* (PMC) Clock from PLL B is selected*/
#define AT91C_PMC_PRES        (0x7 <<  2) /* (PMC) Programmable Clock Prescaler*/
#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) /* (PMC) Selected clock*/
#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) /* (PMC) Selected clock divided by 2*/
#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) /* (PMC) Selected clock divided by 4*/
#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) /* (PMC) Selected clock divided by 8*/
#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) /* (PMC) Selected clock divided by 16*/
#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) /* (PMC) Selected clock divided by 32*/
#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) /* (PMC) Selected clock divided by 64*/
#define AT91C_PMC_MDIV        (0x3 <<  8) /* (PMC) Master Clock Division*/
#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) /* (PMC) The master clock and the processor clock are the same*/
#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock*/
#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock*/
#define 	AT91C_PMC_MDIV_4                    (0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock*/
/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------*/
#define AT91C_PMC_MOSCS       (0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask*/
#define AT91C_PMC_LOCKA       (0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask*/
#define AT91C_PMC_LOCKB       (0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask*/
#define AT91C_PMC_MCKRDY      (0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK0RDY     (0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK1RDY     (0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK2RDY     (0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK3RDY     (0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK4RDY     (0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK5RDY     (0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK6RDY     (0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask*/
#define AT91C_PMC_PCK7RDY     (0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask*/
/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/


/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Clock Generator Controler*/
/* ******************************************************************************/
/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------*/
#define AT91C_CKGR_MOSCEN     (0x1 <<  0) /* (CKGR) Main Oscillator Enable*/
#define AT91C_CKGR_OSCTEST    (0x1 <<  1) /* (CKGR) Oscillator Test*/
#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) /* (CKGR) Main Oscillator Start-up Time*/
/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------*/
#define AT91C_CKGR_MAINF      (0xFFFF <<  0) /* (CKGR) Main Clock Frequency*/
#define AT91C_CKGR_MAINRDY    (0x1 << 16) /* (CKGR) Main Clock Ready*/
/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------*/
#define AT91C_CKGR_DIVA       (0xFF <<  0) /* (CKGR) Divider Selected*/
#define 	AT91C_CKGR_DIVA_0                    (0x0) /* (CKGR) Divider output is 0*/
#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) /* (CKGR) Divider is bypassed*/
#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) /* (CKGR) PLL A Counter*/
#define AT91C_CKGR_OUTA       (0x3 << 14) /* (CKGR) PLL A Output Frequency Range*/
#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet*/
#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet*/
#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet*/
#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet*/
#define AT91C_CKGR_MULA       (0x7FF << 16) /* (CKGR) PLL A Multiplier*/
#define AT91C_CKGR_SRCA       (0x1 << 29) /* (CKGR) PLL A Source*/
/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------*/