at91rm9200_sys.h

ARM板驱动程序源代码

	AT91_REG	 PIOD_PSR; 	/* PIO Status Register*/
	AT91_REG	 Reserved27[1]; 	//
	AT91_REG	 PIOD_OER; 	/* Output Enable Register*/
	AT91_REG	 PIOD_ODR; 	/* Output Disable Registerr*/
	AT91_REG	 PIOD_OSR; 	/* Output Status Register*/
	AT91_REG	 Reserved28[1]; 	//
	AT91_REG	 PIOD_IFER; 	/* Input Filter Enable Register*/
	AT91_REG	 PIOD_IFDR; 	/* Input Filter Disable Register*/
	AT91_REG	 PIOD_IFSR; 	/* Input Filter Status Register*/
	AT91_REG	 Reserved29[1]; 	//
	AT91_REG	 PIOD_SODR; 	/* Set Output Data Register*/
	AT91_REG	 PIOD_CODR; 	/* Clear Output Data Register*/
	AT91_REG	 PIOD_ODSR; 	/* Output Data Status Register*/
	AT91_REG	 PIOD_PDSR; 	/* Pin Data Status Register*/
	AT91_REG	 PIOD_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 PIOD_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 PIOD_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 PIOD_ISR; 	/* Interrupt Status Register*/
	AT91_REG	 PIOD_MDER; 	/* Multi-driver Enable Register*/
	AT91_REG	 PIOD_MDDR; 	/* Multi-driver Disable Register*/
	AT91_REG	 PIOD_MDSR; 	/* Multi-driver Status Register*/
	AT91_REG	 Reserved30[1]; 	//
	AT91_REG	 PIOD_PPUDR; 	/* Pull-up Disable Register*/
	AT91_REG	 PIOD_PPUER; 	/* Pull-up Enable Register*/
	AT91_REG	 PIOD_PPUSR; 	/* Pad Pull-up Status Register*/
	AT91_REG	 Reserved31[1]; 	//
	AT91_REG	 PIOD_ASR; 	/* Select A Register*/
	AT91_REG	 PIOD_BSR; 	/* Select B Register*/
	AT91_REG	 PIOD_ABSR; 	/* AB Select Status Register*/
	AT91_REG	 Reserved32[9]; 	//
	AT91_REG	 PIOD_OWER; 	/* Output Write Enable Register*/
	AT91_REG	 PIOD_OWDR; 	/* Output Write Disable Register*/
	AT91_REG	 PIOD_OWSR; 	/* Output Write Status Register*/
	AT91_REG	 Reserved33[85]; 	//
	AT91_REG	 PMC_SCER; 	/* System Clock Enable Register*/
	AT91_REG	 PMC_SCDR; 	/* System Clock Disable Register*/
	AT91_REG	 PMC_SCSR; 	/* System Clock Status Register*/
	AT91_REG	 Reserved34[1]; 	//
	AT91_REG	 PMC_PCER; 	/* Peripheral Clock Enable Register*/
	AT91_REG	 PMC_PCDR; 	/* Peripheral Clock Disable Register*/
	AT91_REG	 PMC_PCSR; 	/* Peripheral Clock Status Register*/
	AT91_REG	 Reserved35[1]; 	//
	AT91_REG	 CKGR_MOR; 	/* Main Oscillator Register*/
	AT91_REG	 CKGR_MCFR; 	/* Main Clock  Frequency Register*/
	AT91_REG	 CKGR_PLLAR; 	/* PLL A Register*/
	AT91_REG	 CKGR_PLLBR; 	/* PLL B Register*/
	AT91_REG	 PMC_MCKR; 	/* Master Clock Register*/
	AT91_REG	 Reserved36[3]; 	//
	AT91_REG	 PMC_PCKR[8]; 	/* Programmable Clock Register*/
	AT91_REG	 PMC_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 PMC_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 PMC_SR; 	/* Status Register*/
	AT91_REG	 PMC_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 Reserved37[36]; 	//
	AT91_REG	 ST_CR; 	/* Control Register*/
	AT91_REG	 ST_PIMR; 	/* Period Interval Mode Register*/
	AT91_REG	 ST_WDMR; 	/* Watchdog Mode Register*/
	AT91_REG	 ST_RTMR; 	/* Real-time Mode Register*/
	AT91_REG	 ST_SR; 	/* Status Register*/
	AT91_REG	 ST_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 ST_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 ST_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 ST_RTAR; 	/* Real-time Alarm Register*/
	AT91_REG	 ST_CRTR; 	/* Current Real-time Register*/
	AT91_REG	 Reserved38[54]; 	//
	AT91_REG	 RTC_CR; 	/* Control Register*/
	AT91_REG	 RTC_MR; 	/* Mode Register*/
	AT91_REG	 RTC_TIMR; 	/* Time Register*/
	AT91_REG	 RTC_CALR; 	/* Calendar Register*/
	AT91_REG	 RTC_TIMALR; 	/* Time Alarm Register*/
	AT91_REG	 RTC_CALALR; 	/* Calendar Alarm Register*/
	AT91_REG	 RTC_SR; 	/* Status Register*/
	AT91_REG	 RTC_SCCR; 	/* Status Clear Command Register*/
	AT91_REG	 RTC_IER; 	/* Interrupt Enable Register*/
	AT91_REG	 RTC_IDR; 	/* Interrupt Disable Register*/
	AT91_REG	 RTC_IMR; 	/* Interrupt Mask Register*/
	AT91_REG	 RTC_VER; 	/* Valid Entry Register*/
	AT91_REG	 Reserved39[52]; 	//
	AT91_REG	 MC_RCR; 	/* MC Remap Control Register*/
	AT91_REG	 MC_ASR; 	/* MC Abort Status Register*/
	AT91_REG	 MC_AASR; 	/* MC Abort Address Status Register*/
	AT91_REG	 Reserved40[1]; 	//
	AT91_REG	 MC_PUIA[16]; 	/* MC Protection Unit Area*/
	AT91_REG	 MC_PUP; 	/* MC Protection Unit Peripherals*/
	AT91_REG	 MC_PUER; 	/* MC Protection Unit Enable Register*/
	AT91_REG	 Reserved41[2]; 	//
	AT91_REG	 EBI_CSA; 	/* Chip Select Assignment Register*/
	AT91_REG	 EBI_CFGR; 	/* Configuration Register*/
	AT91_REG	 Reserved42[2]; 	//
	AT91_REG	 EBI_SMC2_CSR[8]; 	/* SMC2 Chip Select Register*/
	AT91_REG	 EBI_SDRC_MR; 	/* SDRAM Controller Mode Register*/
	AT91_REG	 EBI_SDRC_TR; 	/* SDRAM Controller Refresh Timer Register*/
	AT91_REG	 EBI_SDRC_CR; 	/* SDRAM Controller Configuration Register*/
	AT91_REG	 EBI_SDRC_SRR; 	/* SDRAM Controller Self Refresh Register*/
	AT91_REG	 EBI_SDRC_LPR; 	/* SDRAM Controller Low Power Register*/
	AT91_REG	 EBI_SDRC_IER; 	/* SDRAM Controller Interrupt Enable Register*/
	AT91_REG	 EBI_SDRC_IDR; 	/* SDRAM Controller Interrupt Disable Register*/
	AT91_REG	 EBI_SDRC_IMR; 	/* SDRAM Controller Interrupt Mask Register*/
	AT91_REG	 EBI_SDRC_ISR; 	/* SDRAM Controller Interrupt Mask Register*/
	AT91_REG	 Reserved43[3]; 	//
	AT91_REG	 EBI_BFC_MR; 	/* BFC Mode Register*/
} AT91S_SYS, *AT91PS_SYS;

#else

/* Offsets from AT91C_BASE_SYS */
#define AIC_SMR		(0) /* Source Mode Register*/
#define AIC_SVR		(128) /* Source Vector Register*/
#define AIC_IVR		(256) /* IRQ Vector Register*/
#define AIC_FVR		(260) /* FIQ Vector Register*/
#define AIC_ISR		(264) /* Interrupt Status Register*/
#define AIC_IPR		(268) /* Interrupt Pending Register*/
#define AIC_IMR		(272) /* Interrupt Mask Register*/
#define AIC_CISR	(276) /* Core Interrupt Status Register*/
#define AIC_IECR	(288) /* Interrupt Enable Command Register*/
#define AIC_IDCR	(292) /* Interrupt Disable Command Register*/
#define AIC_ICCR	(296) /* Interrupt Clear Command Register*/
#define AIC_ISCR	(300) /* Interrupt Set Command Register*/
#define AIC_EOICR	(304) /* End of Interrupt Command Register*/
#define AIC_SPU		(308) /* Spurious Vector Register*/
#define AIC_DCR		(312) /* Debug Control Register (Protect)*/
#define AIC_FFER	(320) /* Fast Forcing Enable Register*/
#define AIC_FFDR	(324) /* Fast Forcing Disable Register*/
#define AIC_FFSR	(328) /* Fast Forcing Status Register*/

/* Offsets from AT91C_BASE_SYS */
#define DBGU_CR		(0x200 + 0) /* Control Register*/
#define DBGU_MR		(0x200 + 4) /* Mode Register*/
#define DBGU_IER	(0x200 + 8) /* Interrupt Enable Register*/
#define DBGU_IDR	(0x200 + 12) /* Interrupt Disable Register*/
#define DBGU_IMR	(0x200 + 16) /* Interrupt Mask Register*/
#define DBGU_CSR	(0x200 + 20) /* Channel Status Register*/
#define DBGU_RHR	(0x200 + 24) /* Receiver Holding Register*/
#define DBGU_THR	(0x200 + 28) /* Transmitter Holding Register*/
#define DBGU_BRGR	(0x200 + 32) /* Baud Rate Generator Register*/
#define DBGU_C1R	(0x200 + 64) /* Chip ID1 Register*/
#define DBGU_C2R	(0x200 + 68) /* Chip ID2 Register*/
#define DBGU_FNTR	(0x200 + 72) /* Force NTRST Register*/
#define DBGU_RPR	(0x200 + 256) /* Receive Pointer Register*/
#define DBGU_RCR	(0x200 + 260) /* Receive Counter Register*/
#define DBGU_TPR	(0x200 + 264) /* Transmit Pointer Register*/
#define DBGU_TCR	(0x200 + 268) /* Transmit Counter Register*/
#define DBGU_RNPR	(0x200 + 272) /* Receive Next Pointer Register*/
#define DBGU_RNCR	(0x200 + 276) /* Receive Next Counter Register*/
#define DBGU_TNPR	(0x200 + 280) /* Transmit Next Pointer Register*/
#define DBGU_TNCR	(0x200 + 284) /* Transmit Next Counter Register*/
#define DBGU_PTCR	(0x200 + 288) /* PDC Transfer Control Register*/
#define DBGU_PTSR	(0x200 + 292) /* PDC Transfer Status Register*/

#endif /* __ASSEMBLY*/


/* ******************************************************************************/
/*              SOFTWARE API DEFINITION  FOR Memory Controller Interface*/
/* ******************************************************************************/
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------*/
#define AT91C_MC_RCB          (0x1 <<  0) /* (MC) Remap Command Bit*/
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------*/
#define AT91C_MC_UNDADD       (0x1 <<  0) /* (MC) Undefined Addess Abort Status*/
#define AT91C_MC_MISADD       (0x1 <<  1) /* (MC) Misaligned Addess Abort Status*/
#define AT91C_MC_MPU          (0x1 <<  2) /* (MC) Memory protection Unit Abort Status*/
#define AT91C_MC_ABTSZ        (0x3 <<  8) /* (MC) Abort Size Status*/
#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) /* (MC) Byte*/
#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) /* (MC) Half-word*/
#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) /* (MC) Word*/
#define AT91C_MC_ABTTYP       (0x3 << 10) /* (MC) Abort Type Status*/
#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) /* (MC) Data Read*/
#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) /* (MC) Data Write*/
#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) /* (MC) Code Fetch*/
#define AT91C_MC_MST0         (0x1 << 16) /* (MC) Master 0 Abort Source*/
#define AT91C_MC_MST1         (0x1 << 17) /* (MC) Master 1 Abort Source*/
#define AT91C_MC_SVMST0       (0x1 << 24) /* (MC) Saved Master 0 Abort Source*/
#define AT91C_MC_SVMST1       (0x1 << 25) /* (MC) Saved Master 1 Abort Source*/
/* -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------*/
#define AT91C_MC_PROT         (0x3 <<  0) /* (MC) Protection*/
#define 	AT91C_MC_PROT_PNAUNA               (0x0) /* (MC) Privilege: No Access, User: No Access*/
#define 	AT91C_MC_PROT_PRWUNA               (0x1) /* (MC) Privilege: Read/Write, User: No Access*/
#define 	AT91C_MC_PROT_PRWURO               (0x2) /* (MC) Privilege: Read/Write, User: Read Only*/
#define 	AT91C_MC_PROT_PRWURW               (0x3) /* (MC) Privilege: Read/Write, User: Read/Write*/
#define AT91C_MC_SIZE         (0xF <<  4) /* (MC) Internal Area Size*/