sysalib.s

ARM板驱动程序源代码

	LDR	r1, =INTEGRATOR_HDR_BASE
	LDR	r2, [r1, #INTEGRATOR_HDR_OSC_OFFSET]
	AND	r2, r2, #(3 << 23)
	CMP	r2, #(1 << 23)
	BNE	clock1

#if defined(CPU_920T) || defined(CPU_920T_T) || \
    defined(CPU_940T) || defined(CPU_940T_T)
	/*
	 * if HDR_OSC indicates (bits[23:24] = 01), set
	 * implementation-specific bits in the MMU control register - set
	 * asynchronous mode.
	 */

	MRC	CP_MMU, 0, r2, c1, c0, 0
	ORR	r2, r2, #MMUCR_ASYNC
	MCR	CP_MMU, 0, r2, c1, c0, 0
#endif

clock1:
	/* If bits[23:24] were 0, set asynchronous mode in HDR_CTRL */

	LDRLT	r2, [r1, #INTEGRATOR_HDR_CTRL_OFFSET]
	BICLT	r2, r2, #INTEGRATOR_HDR_CTRL_FASTBUS
	STRLT	r2, [r1, #INTEGRATOR_HDR_CTRL_OFFSET]

	/*
	 * setup default clocks
	 *
	 * Core clock must always be greater than memory clock.
	 *
	 * Read HDR_PROC register, if this is non zero then there is no
	 * coprocessor, in this case use the default settings. First,
	 * load the default settings.
	 */

	LDR	r2, =INTEGRATOR_HDR_OSC_DFLT_VAL
	LDR	r1, =INTEGRATOR_HDR_BASE
	LDR	r3, [r1, #INTEGRATOR_HDR_PROC_OFFSET]
	CMP	r3, #0
	BNE	write_clock
	
	/*
	 * HDR_PROC was zero => there is a coprocessor. Get the processor ID.
	 *
	 * If the processor type is not recognised then the default settings
	 * will be used.
	 *
	 * For safety's sake, make the following conditional upon there being a
	 * coprocessor in the CPU.
	 */

#if defined(CPU_720T)  || defined(CPU_720T_T)  || \
    defined(CPU_740T)  || defined(CPU_740T_T)  || \
    defined(CPU_920T)  || defined(CPU_920T_T)  || \
    defined(CPU_940T)  || defined(CPU_940T_T)  || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_966ES) || defined(CPU_966ES_T)
	MRC	CP_MMU, 0, r1, c0, c0, 0
	MOV	r3, r1, LSL #16
	MOV	r3, r3, LSR #20		/* move bits 15-3 to 12-0 */

	CMP	r3, #0x720		/* is this a 720 */
	LDREQ	r2, =INTEGRATOR_HDR_OSC_720T_VAL
	BEQ	write_clock

	CMP	r3, #0x740		/* is this a 740 */
        LDREQ   r2, =INTEGRATOR_HDR_OSC_740T_VAL
	BEQ     write_clock

	CMP	r3, #0x940		/* is this a 940 */
	LDREQ	r2, =INTEGRATOR_HDR_OSC_940T_VAL
	BEQ	write_clock

	LDR	r12, =0x946
	CMP	r3, r12			/* is this a 946ES */
	LDREQ	r2, =INTEGRATOR_HDR_OSC_946ES_VAL
	BEQ	write_clock

	CMP	r3, #0x920		/* is this a 920 */
	LDREQ	r2, =INTEGRATOR_HDR_OSC_920T_VAL
	BEQ	write_clock

	MOV	r1, r3, LSR #4		/* is this a 966 */
	CMP	r1, #0x96
	BNE	write_clock
	AND	r1, r3, #0xF
	CMP	r1, #6
	LDREQ	r2, =INTEGRATOR_HDR_OSC_966ES_VAL
#endif /* defined(CPU_720T/740T/920T/940T/966ES) */

write_clock:
	/* Write clock settings */

	LDR	r1, =INTEGRATOR_HDR_BASE
	LDR	r3, =0xA05F
	STR	r3, [r1, #INTEGRATOR_HDR_LOCK_OFFSET]
	STR	r2, [r1, #INTEGRATOR_HDR_OSC_OFFSET]
	MOV	r2, #0
	STR	r2, [r1, #INTEGRATOR_HDR_LOCK_OFFSET]

	/* Set up System BUS and PCI clocks */

	LDR	r1, =INTEGRATOR_SC_BASE
	STR	r3, [r1, #INTEGRATOR_SC_LOCK_OFFSET]
	LDR	r2, =(INTEGRATOR_SC_OSC_SYS_20MHz | INTEGRATOR_SC_OSC_PCI_33MHz)
	STR	r2, [r1, #INTEGRATOR_SC_OSC_OFFSET]
	MOV	r2, #0
	STR	r2, [r1, #INTEGRATOR_SC_LOCK_OFFSET]

	/* Initialize static memory. */

	MOV	r1, #INTEGRATOR_EBI_BASE
	
	/* CS0 - ROM (Boot Flash) */

	MOV	r2, #INTEGRATOR_EBI_8_BIT | INTEGRATOR_EBI_WS_3
	STR	r2, [r1, #INTEGRATOR_EBI_CSR0_OFFSET]

	/* CS1 - Flash (Application Flash) */

	MOV	r2, #INTEGRATOR_EBI_32_BIT | INTEGRATOR_EBI_WS_3
	STR	r2, [r1, #INTEGRATOR_EBI_CSR1_OFFSET]

	/* CS2 - SSRAM (Not on Rev A Boards) */

	MOV	r2, #INTEGRATOR_EBI_32_BIT | INTEGRATOR_EBI_WRITE_ENABLE | \
		     INTEGRATOR_EBI_SYNC | INTEGRATOR_EBI_WS_2
	STR	r2, [r1, #INTEGRATOR_EBI_CSR2_OFFSET]

	/* CS3 - Unused (Set up for debug) */

	MOV	r2, #INTEGRATOR_EBI_8_BIT | INTEGRATOR_EBI_WRITE_ENABLE
	STR	r2, [r1, #INTEGRATOR_EBI_CSR3_OFFSET]
#endif

	/* set initial stack pointer so stack grows down from start of code */

	ADR	sp, FUNC(sysInit)		/* initialise stack pointer */

	/* now call usrInit */

	MOV	fp, #0			/* initialise frame pointer */
/*	MOV	r0, #BOOT_WARM_AUTOBOOT	*//* pass startType */

#if	(ARM_THUMB)
	LDR	r12, L$_usrInit
	BX	r12
#else
	B	FUNC(usrInit)
#endif	/* (ARM_THUMB) */

/*******************************************************************************
*
* sysIntStackSplit - split interrupt stack and set interrupt stack pointers
*
* This routine is called, via a function pointer, during kernel
* initialisation.  It splits the allocated interrupt stack into IRQ and
* SVC-mode stacks and sets the processor's IRQ stack pointer. Note that
* the pointer passed points to the bottom of the stack allocated i.e.
* highest address+1.
*
* IRQ stack needs 6 words per nested interrupt;
* SVC-mode will need a good deal more for the C interrupt handlers.
* For now, use ratio 1:7 with any excess allocated to the SVC-mode stack
* at the lowest address.
*
* Note that FIQ is not handled by VxWorks so no stack is allocated for it.
*
* The stacks and the variables that describe them look like this.
* .CS
*
*         - HIGH MEMORY -
*     ------------------------ <--- vxIrqIntStackBase (r0 on entry)
*     |                      |
*     |       IRQ-mode       |
*     |    interrupt stack   |
*     |                      |
*     ------------------------ <--{ vxIrqIntStackEnd
*     |                      |    { vxSvcIntStackBase
*     |       SVC-mode       |
*     |    interrupt stack   |
*     |                      |
*     ------------------------ <--- vxSvcIntStackEnd
*         - LOW  MEMORY -
* .CE
*
* NOTE: This routine should not be called by the user.

* void sysIntStackSplit
*     (
*     char *pBotStack   /@ pointer to bottom of interrupt stack @/
*     long size		/@ size of stack @/
*     )

*/

_ARM_FUNCTION_CALLED_FROM_C(sysIntStackSplit)

	/*
	 * r0 = base of space allocated for stacks (i.e. highest address)
	 * r1 = size of space
	 */

	SUB	r2, r0, r1			/* r2->lowest usable address */
	LDR	r3, L$_vxSvcIntStackEnd
	STR	r2, [r3]			/*  == end of SVC-mode stack */
	SUB	r2, r0, r1, ASR #3		/* leave 1/8 for IRQ */
	LDR	r3, L$_vxSvcIntStackBase
	STR	r2, [r3]

	/* now allocate IRQ stack, setting irq_sp */

	LDR	r3, L$_vxIrqIntStackEnd
	STR	r2, [r3]
	LDR	r3, L$_vxIrqIntStackBase
	STR	r0, [r3]

	MRS	r2, cpsr
	BIC	r3, r2, #MASK_MODE
	ORR	r3, r3, #MODE_IRQ32 | I_BIT	/* set irq_sp */
	MSR	cpsr, r3
	MOV	sp, r0

	/* switch back to original mode and return */

	MSR	cpsr, r2

#if	(ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif	/* (ARM_THUMB) */
		
/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor preforming substitution
 */

	.balign	4

L$_vxSvcIntStackBase:
	.long	VAR(vxSvcIntStackBase)

L$_vxSvcIntStackEnd:
	.long	VAR(vxSvcIntStackEnd)

L$_vxIrqIntStackBase:
	.long	VAR(vxIrqIntStackBase)

L$_vxIrqIntStackEnd:
	.long	VAR(vxIrqIntStackEnd)

#if	(ARM_THUMB)
L$_usrInit:
	.long	FUNC(usrInit)
#endif	/* (ARM_THUMB) */

#if defined(CPU_720T) || defined(CPU_720T_T) || \
    defined(CPU_740T) || defined(CPU_740T_T)
L$_sysCacheSwapVar:
	.long   sysCacheSwapVar
#endif
#if defined(CPU_940T) || defined(CPU_940T_T)

L$_sysCacheUncachedAdrs:
	.long   SYS_CACHE_UNCACHED_ADRS
#endif