target.nr

ARM板驱动程序源代码

.SS "WindML Support"

WindML 2.0 is supported on the integrator7tdmi.  Other integrator
versions have not been tested with WindML and no WindML support is
included for those BSPs.

If the BSP is configured with INCLUDE_WINDML defined, support for
WindML 2.0 is included.  Otherwise, WindML will not be
enabled.  Additionally, the WindML drivers need to be configured
properly as described in the "WindML Programmer's Guide",  Part#
DOC-13632-ND-02.

Modify the file target/src/ugl/config/uglInit.h as follows:

.bS
 #define INCLUDE_IGS_GRAPHICS
 #define INCLUDE_CUSTOM_KEYBOARD
 #define INCLUDE_CUSTOM_POINTER
 #define JP3_ON
.bE

Because this configuration uses custom keyboard and mouse drivers, the
file target/h/ugl/config/uglCustom.h must be created from the template
in the same directory.  An excerpt from this file is shown below:

.bS
  /* Custom keyboard */
  #ifdef INCLUDE_CUSTOM_KEYBOARD
  #define INCLUDE_UGL_INPUT
  #define SYS_KEYBOARD_NAME     "/keyboard/0"
  
  /* Name of the function to create the keyboard device */
  extern STATUS                      ambaKbdDevCreate(char *name);
  #define SYS_KEYBOARD_CREATE        ambaKbdDevCreate
  
  /* Name of the function to initialize the keyboard device */
  
  extern UGL_INPUT_DEVICE_ID uglAmbaKbdInit (char * name,
                                     UGL_EVENT_SERVICE_ID eventServiceId);
  #define UGL_KEYBOARD_INIT	   uglPcKbdInit
  #endif /* INCLUDE_CUSTOM_KEYBOARD */
  
  /* Custom pointer */
  #ifdef INCLUDE_CUSTOM_POINTER
  #ifndef INCLUDE_UGL_INPUT
  #define INCLUDE_UGL_INPUT
  #endif /* INCLUDE_UGL_INPUT */
  
  #define SYS_POINTER_NAME     "/ambaPtr/0"
  
  /* Name of the function to create the pointer device */
  extern STATUS                      ambaPs2DevCreate(char *name);
  #define SYS_POINTER_CREATE	   ambaPs2DevCreate
  
  /* Name of the function to initialize the pointer device */
  
  extern UGL_INPUT_DEVICE_ID uglPs2PtrInit (char * name,
                                     UGL_EVENT_SERVICE_ID eventServiceId);
  #define UGL_POINTER_INIT	   uglPs2PtrInit
  #endif /* INCLUDE_CUSTOM_POINTER */

.bE

Also, make sure, IGS is compiled into the ARM libraries.
The 'igs' directory may need to be added to the Makefile
'target/src/ugl/driver/graphics/Makefile' as follows:

.bS
  ifeq ($(CPU), ARMARCH4)
      CPU_SUBDIRS = arm igs
  endif
  ifeq ($(CPU), ARMARCH5)
      CPU_SUBDIRS = arm igs
  endif
.bE

The macro USE_BSP_API must be defined.  This can be done by inserting
'CPU==ARMARCH4' in the file target/h/ugl/driver/graphics/igs/udigs.h as
follows:


.bS
  #if ((CPU == MIPS32) || (CPU == MIPS64) || (CPU == ARMARCH4) \
    || (CPU == ARMARCH5))
  #define USE_BSP_API
  #endif
.bE

.SH "HARDWARE DETAILS"

.SS "Devices"
The device drivers included are:

    primeCellSio.c - PrimeCell UART driver.

If Flash support is configured then the following drivers are included:

   nvRamToFlash.c - NVRAM-to-Flash memory library

.SS "Shared memory"
This BSP has not been tested with shared memory, and there is no
BSP-specific support for test-and-set primitives.  The vxTas()
primitive is provided in the architecture-specific code to allow access
to the ARM SWPB instruction.  For further information, see the vxTas()
reference entry.

.SS "Interrupts"

22 interrupt levels are provided:
    0 Soft interrupt
    1 UART 0
    2 UART 1
    3 Keyboard
    4 Mouse
    5 Timer 0
    6 Timer 1
    7 Timer 2
    8 Real time clock
    9 Logic module 0
   10 Logic module 1
   11 Logic module 2
   12 Logic module 3
   13 PCI bus (INTA#)
   14 PCI bus (INTB#)
   15 PCI bus (INTC#)
   16 PCI bus (INTD#)
   17 V3 PCI bridge
   18 CompactPCI auxiliary interrupt (DEG#)
   19 CompactPCI auxiliary interrupt (ENUM#)
   20 PCI local bus fault
   21 External AutoPC

Only interrupt levels 1, 2, 5, 6, 13, 14, 15 and 16 are used by default
in this BSP.  Interrupt connection, enabling and disabling are
performed using the standard intArchLib routines.  The interrupt
controller driver is provided in ambaIntrCtl.c.

.SS "Serial Configuration"

There are two serial ports on the board, provided by two PrimeCell UARTs.
The default configuration is 9600 baud, 8 data bits, no parity, 1 stop
bit.

The driver code in primecellSio.c/.h is a modified version of the
standard VxWorks ambaSio driver.  Documentation for the PrimeCell UART
is on the ARM web site.

The two main differences are as follows:

The PrimeCell SIO has five separate interrupt signal lines.  Four of
these correspond to different types of interrupt; the fifth is a
combined signal, which is used on the Integrator to provide a single
interrupt source for each UART.

There are two separate interrupt signals for received data: one is
generated when the received buffer is more than half full; the other
when no data is received for 32 UART clocks.

.SS "SCSI Configuration"
This BSP does not support SCSI.

.SS "Network Configuration"
This BSP provides network support for PCI Dec 21x4x network cards.

.SS "VME Access"
The board is a standalone board: VME is not supported.

.SS "PCI Access"
This BSP supports the PCI bus and has been tested with network
expansion cards.  PCI to PCI bridge functionality is not implemented.

.SS "Boot Devices"
The default boot image provided with this BSP does not provide a
mechanism for loading a VxWorks kernel.


.SH "SPECIAL CONSIDERATIONS"
.SS "CPU Speed/Timers"

All clocks are derived from various VCOs and dividers, which can be
modified under software control.  Clock values are read throuh the 
coprocessor are set according to the header fitted (cf. romInit.s).

.SS "Special routines"
The routine sysLedsReadWrite() is used to control the LEDs on the
board.  Use of the LEDs is mutually exclusive with use of the parallel
port due to a restriction in the hardware.  For further information,
see the reference entry for this routine.

.SS "Divide by Zero Exception"
The ARM architecture does not provide for an integer divide by zero
exception.  Consequently, no exception is generated when an integer
divide by zero operation is performed programmatically.

.SS "Multiple core module support"
Support is provided for only one core module.

.SH "BOARD LAYOUT"
The diagrams below show the relevant jumpers for VxWorks
configuration.
.bS

______________________________________________________________________________
|               +---+ +---+ +---+ +---+    J15                               |
|         LOGIC | U | | U | | U | | U |    +-+                             +-+
|          +-+  |11 | |12 | |13 | |14 |    | |                          J21| |
|+-------+ | |  +---+ +---+ +---+ +---+    | |                             | |
|| J12   + | |  +---+ +---+ +---+ +---+    | |                             +-+
|+-------+ | |  | U | | U | | U | | U |    | |                       S3   S2 |
|          +-+  |15 | |16 | |17 | |18 |    | |                               |
|               +---+ +---+ +---+ +---+    | |                               |
|               +-----+                    | |                               |
|           U34 |SRAM |   ----EXPM----     +-+                               |
|               +-----+             +---+                                    |
|--+            +-----+             |U19|                                    |
|  |ALPHA   U35 |SRAM |             +---+                                    |
|  |DISPLAY     +-----+           +-----+                                    |
|--+                              | V3  |                                    |
|                                 +-----+                                    |
|    +----------------------------+       +-+ +-+ +-+                        |
|    |                            |       | | | | | |                       +--+
|    |                            |       |P| |P| |P|                       |C |
|    |               +-------+    |       |C| |C| |C|                       |O |
|    |               |  FPGA |    |       |I| |I| |I|                       |M |
+-+  | +------+      |       |    |       | | | | | |                       |P |
|A|  | |  CPU |      +-------+    |       |S| |S| |S|                       |A |
|T|  | |      |                   |       |L| |L| |L|                       |C |
|X|  | +----- +                   |       |O| |O| |O|                       |T |
+-+  |                            |       |T| |T| |T|            +--------+ |  |
|    +----------------------------+       | | | | | |            | PCI/PCI| |P |
|KBD                                      +-+ +-+ +-+            | Bridge | |C |
+--+      SERIAL SERIAL                   J9  J10 J11            +--------+ |I |
|  |  S1  +----+ +----+                                                     +--+
|__|______|    |_|    |_____________________    ______________________________|
.bE
    Key:
    S1    4 pole DIL switch
    S2    Reset button
    S3    Standby button

    U11.. Flash memory
    U19   Boot ROM
    J15   Logic module connector (EXPA) 
    EXPM  External bus interface connector
    V3    System bus - PCI bridge

.SH SEE ALSO
.tG "Getting Started,"
.pG "Configuration."

.SH BIBLIOGRAPHY
.I "ARM Integrator/AP User Guide",
.I "ARM Integrator/CM7TDMI User Guide",
.I "ARM Integrator/CM720T User Guide",
.I "ARM Integrator/CM740T User Guide",
.I "ARM Integrator/CM920T User Guide",
.I "ARM Integrator/CM940T User Guide",
.I "ARM Integrator/CM9x6ES Datasheet",
.I "ARM Architecture Reference Manual",
.I "ARM 7TDMI Data Sheet",
.I "ARM 720T Data Sheet",
.I "ARM 740T Data Sheet",
.I "ARM 920T Technical Reference Manual",
.I "ARM 940T Technical Reference Manual",
.I "ARM 966ES Technical Reference Manual",
.I "ARM Reference Peripherals Specification".