📄 vector.asm
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;
; Copyright 2002 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
;
; "@(#) DSP/BIOS 4.80.208 12-06-02 (barracuda-l19)"
;
; ======== vectors.asm ========
; Plug in the entry point at RESET in the interrupt vector table
;
;
; ======== unused ========
; plug inifinite loop -- with nested branches to
; disable interrupts -- for all undefined vectors
;
FLASH_DAT_PTR .equ 0x64000000 ;Flash Data Memory
INT_DAT_PTR .equ 0x00000000 ;Internal Data Memory
DAT_CODE_SIZE .equ 0x000FFFFF ;Internal Data Memory Size
CONST_SIZE .equ 0x0017FFFF ;Internal Data Memory Size
SDRAM_DAT_PTR .equ 0x80000000 ;SDRAM pointer
FLASH_DAT_PTR2 .equ 0x64020000
EMIFA_GCTL .equ 0x01800000
EMIFB_GCTL .equ 0x01A80000
EMIFA_CE0 .equ 0x01800008 ;Address of EMIF CE0 control register address
EMIFA_CE1 .equ 0x01800004 ;Address of EMIF CE1 control register address
EMIFA_CE2 .equ 0x01800010 ;Address of EMIF CE2 control register address
EMIFA_CE3 .equ 0x01800014 ;Address of EMIF CE3 control register address
EMIFB_CE1 .equ 0x01A80004
EMIFB_CE0 .equ 0x01A80008
EMIFB_CE2 .equ 0x01A80010
EMIFB_CE3 .equ 0x01A80014 ;Address of EMIF CE3 control register address
EMIFA_SDRAMCTL .equ 0x01800018
EMIFA_SDRAMREF .equ 0x0180001c
EMIFA_SDRAMEXT .equ 0x01800020
EMIFA_CE1SECCTL .equ 0x01800044
EMIFA_CE0SECCTL .equ 0x01800048
EMIFA_CE2SECCTL .equ 0x01800050
EMIFA_CE3SECCTL .equ 0x01800054
EMIF_GCR_V .equ 0x000523E0 ;0x0000377D ;Address of EMIF global control register value
EMIFA_CE0_V .equ 0x241FC81F ;0x00000040 ;Address of EMIF CE0 control register value
EMIFA_CE1_V .equ 0xffffffD3 ;0x33300F12 ;Address of EMIF CE1 control register value
EMIFA_CE2_V .equ 0xffffff4f
EMIFA_CE3_V .equ 0xC3FCCF0F
EMIF_GCR_VB .equ 0x000323E0
EMIFB_CE0_V .equ 0x10514212 ;0x20B28212 ;
EMIFB_CE1_V .equ 0x24f1D10F ;
EMIFB_CE2_V .equ 0x1191c803 ;75ffff2f
EMIFB_CE3_V .equ 0x4373D71F ;75ffff2f
EMIF_SDCTRL_V .equ 0x57116000 ;0x07B37000 ;Address of EMIF SDRAM control register value
EMIF_SDRP_V .equ 0x0000061A ;0x000004E2 ;Address of EMIF SDRM refresh period register value
.sect "vectors"
; .global _c_int06
.ref _c_int00;, _c_int04, _c_int05, _c_int06, _c_int07, _c_int08, _c_int09, _c_int10, _c_int11, _c_int12, _c_int13, _c_int14, _c_int15
; C entry point
.align 32*8*4 ; must be aligned on 256 word boundary
RESET: B SYSINIT ; start branch to destination function
nop ; fill delay slot
nop
nop
nop
nop
nop
nop
SYSINIT:
MVKL EMIFA_GCTL, A4 ;EMIFA_GCR address -> A4
|| MVKL EMIF_GCR_V, B4
MVKH EMIFA_GCTL, A4
|| MVKH EMIF_GCR_V, B4
STW B4, *A4
MVKL EMIFA_CE0, A4 ;EMIFA_CE0 address -> A4
|| MVKL EMIFA_CE0_V, B4
MVKH EMIFA_CE0, A4
|| MVKH EMIFA_CE0_V, B4
STW B4, *A4
MVKL EMIFA_CE1, A4 ;EMIFA_CE1 address -> A4
|| MVKL EMIFA_CE1_V, B4
MVKH EMIFA_CE1, A4
|| MVKH EMIFA_CE1_V, B4
STW B4, *A4
MVKL EMIFB_GCTL, A4 ;EMIFB_GCR address -> A4
|| MVKL EMIF_GCR_V, B4
MVKH EMIFB_GCTL, A4
|| MVKH EMIFB_CE1_V, B4
STW B4, *A4
MVKL EMIFB_CE1, A4 ;EMIFB_CE1 address -> A4
|| MVKL EMIFB_CE1_V, B4
MVKH EMIFB_CE1, A4
|| MVKH EMIFB_CE1_V, B4
STW B4, *A4
MVKL EMIFB_CE3, A4 ;EMIFB_CE3 address -> A4
|| MVKL EMIFB_CE3_V, B4
MVKH EMIFB_CE3, A4
|| MVKH EMIFB_CE3_V, B4
STW B4, *A4
MVKL EMIFB_CE2, A4 ;EMIF_CE2 address -> A4
|| MVKL EMIFB_CE2_V, B4 ;
MVKH EMIFB_CE2, A4
|| MVKH EMIFB_CE2_V, B4
STW B4, *A4
MVKL EMIFB_CE0, A4 ;EMIF_CE0 address -> A4
|| MVKL EMIFB_CE0_V, B4 ;
MVKH EMIFB_CE0, A4
|| MVKH EMIFB_CE0_V, B4
STW B4, *A4
MVKL EMIFA_SDRAMCTL, A4 ;EMIF_SDCTRL address -> A4
|| MVKL EMIF_SDCTRL_V, B4
MVKH EMIFA_SDRAMCTL, A4
|| MVKH EMIF_SDCTRL_V, B4
STW B4, *A4
MVKL EMIFA_SDRAMREF , A4 ;EMIF_SDRP address -> A4
|| MVKL EMIF_SDRP_V, B4
MVKH EMIFA_SDRAMREF , A4
|| MVKH EMIF_SDRP_V, B4
STW B4, *A4
NOP
MVKL DAT_CODE_SIZE, B0
MVKH DAT_CODE_SIZE, B0
MVKL INT_DAT_PTR, A4
|| MVKL FLASH_DAT_PTR, B4
MVKH INT_DAT_PTR, A4
|| MVKH FLASH_DAT_PTR, B4
;loop:
; LDW *B4++, B5
; NOP 4
; STW B5, *A4++
; SUB B0, 1, B0
; CMPLT 0x0, B0, B1
;[ B1] B loop
;
; NOP 5
; MVKL .S2 _c_int00, B0
; MVKH .S2 _c_int00, B0
; B .S2 B0
; NOP 5
; copy sections
mvkl copyTable, a3 ; load table pointer
mvkh copyTable, a3
copy_section_top:
ldw *a3++, b0 ; byte count
ldw *a3++, a4 ; load ram start address
ldw *a3++, b4 ; load flash start address
nop 4
[!b0] b copy_done ; have we copied all sections?
nop 5
copy_loop:
ldb *B4++,B5
nop 4
stb B5,*A4++
nop 4
[B0] sub b0,1,b0
[B0] b copy_loop
nop 5
b copy_section_top
nop 5
copy_done:
mvkl .S2 _c_int00, B0
mvkh .S2 _c_int00, B0
b .S2 B0
nop 5
;; Table of sections to copy. Format is:
;; word 0: byte count
;; word 1: run address
;; word 2: load address
;; .boot_load don't need to copy, will happen automatically upon dsp reset.
copyTable:
;; .text
.word 0x000068e0
.word 0x00008400
.word 0x64000400
;; .bios
.word 0x00003ec0
.word 0x0000ece0
.word 0x64006ce0
;; .cinit
.word 0x0000121c
.word 0x00012ba0
.word 0x6400aba0
;; .trcdata
.word 0x0000000c
.word 0x00017e6c
.word 0x6400cbb4
;; .rtdx_text
.word 0x00000dc0
.word 0x00015700
.word 0x6400bdc0
;; .gblinit
.word 0x00000034
.word 0x00017dac
.word 0x6400cb80
;; .pinit
.word 0x0000000c
.word 0x00017e78
.word 0x6400cbc0
;; .hwi_vec
.word 0x00000200
.word 0x00016800
.word 0x6400cc00
;; .sysinit
.word 0x000003a0
.word 0x00017660
.word 0x6400ce00
;; .const
.word 0x0000008a
.word 0x00017cc8
.word 0x6400d1a0
;; .sysinit
.word 0
.word 0
.word 0
;; end of table
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0⌨️ 快捷键说明
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