verilog_led.v

来自「DE2实验开发板的将32位数据转换为八个七段译码并显示」· Verilog 代码 · 共 185 行

module Verilog_led(A_rbuf,led7s);

output[55:0]led7s;
reg[55:0] led7s;

input[31:0]A_rbuf;

always@(A_rbuf[3:0])
 begin
	case(A_rbuf[3:0])
	4'd0:led7s[6:0]=7'b1000000;
	4'd1:led7s[6:0]=7'b1111001;
	4'd2:led7s[6:0]=7'b0100100;
	4'd3:led7s[6:0]=7'b0110000;
	4'd4:led7s[6:0]=7'b0011001;
	4'd5:led7s[6:0]=7'b0010010;
	4'd6:led7s[6:0]=7'b0000010;
	4'd7:led7s[6:0]=7'b1111000;
	4'd8:led7s[6:0]=7'b0000000;
	4'd9:led7s[6:0]=7'b0010000;
	4'd10:led7s[6:0]=7'b0001000;
	4'd11:led7s[6:0]=7'b0000011;
	4'd12:led7s[6:0]=7'b1000110;
	4'd13:led7s[6:0]=7'b0100001;
	4'd14:led7s[6:0]=7'b0000110;
	4'd15:led7s[6:0]=7'b0001110;
	default:led7s[6:0]=7'bx;
	endcase
end
always@(A_rbuf[7:4])
 begin
	case(A_rbuf[7:4])
	4'd0:led7s[13:7]=7'b1000000;
	4'd1:led7s[13:7]=7'b1111001;
	4'd2:led7s[13:7]=7'b0100100;
	4'd3:led7s[13:7]=7'b0110000;
	4'd4:led7s[13:7]=7'b0011001;
	4'd5:led7s[13:7]=7'b0010010;
	4'd6:led7s[13:7]=7'b0000010;
	4'd7:led7s[13:7]=7'b1111000;
	4'd8:led7s[13:7]=7'b0000000;
	4'd9:led7s[13:7]=7'b0010000;
	4'd10:led7s[13:7]=7'b0001000;
	4'd11:led7s[13:7]=7'b0000011;
	4'd12:led7s[13:7]=7'b1000110;
	4'd13:led7s[13:7]=7'b0100001;
	4'd14:led7s[13:7]=7'b0000110;
	4'd15:led7s[13:7]=7'b0001110;
	default:led7s[13:7]=7'bx;
	endcase
end
always@(A_rbuf[11:8])
 begin
	case(A_rbuf[11:8])
	4'd0:led7s[20:14]=7'b1000000;
	4'd1:led7s[20:14]=7'b1111001;
	4'd2:led7s[20:14]=7'b0100100;
	4'd3:led7s[20:14]=7'b0110000;
	4'd4:led7s[20:14]=7'b0011001;
	4'd5:led7s[20:14]=7'b0010010;
	4'd6:led7s[20:14]=7'b0000010;
	4'd7:led7s[20:14]=7'b1111000;
	4'd8:led7s[20:14]=7'b0000000;
	4'd9:led7s[20:14]=7'b0010000;
	4'd10:led7s[20:14]=7'b0001000;
	4'd11:led7s[20:14]=7'b0000011;
	4'd12:led7s[20:14]=7'b1000110;
	4'd13:led7s[20:14]=7'b0100001;
	4'd14:led7s[20:14]=7'b0000110;
	4'd15:led7s[20:14]=7'b0001110;
	default:led7s[20:14]=7'bx;
	endcase
 end
always@(A_rbuf[15:12])
 begin
	case(A_rbuf[15:12])
	4'd0:led7s[27:21]=7'b1000000;
	4'd1:led7s[27:21]=7'b1111001;
	4'd2:led7s[27:21]=7'b0100100;
	4'd3:led7s[27:21]=7'b0110000;
	4'd4:led7s[27:21]=7'b0011001;
	4'd5:led7s[27:21]=7'b0010010;
	4'd6:led7s[27:21]=7'b0000010;
	4'd7:led7s[27:21]=7'b1111000;
	4'd8:led7s[27:21]=7'b0000000;
	4'd9:led7s[27:21]=7'b0010000;
	4'd10:led7s[27:21]=7'b0001000;
	4'd11:led7s[27:21]=7'b0000011;
	4'd12:led7s[27:21]=7'b1000110;
	4'd13:led7s[27:21]=7'b0100001;
	4'd14:led7s[27:21]=7'b0000110;
	4'd15:led7s[27:21]=7'b0001110;
	default:led7s[27:21]=7'bx;
	endcase
 end
always@(A_rbuf[19:16])
 begin
	case(A_rbuf[19:16])
	4'd0:led7s[34:28]=7'b1000000;
	4'd1:led7s[34:28]=7'b1111001;
	4'd2:led7s[34:28]=7'b0100100;
	4'd3:led7s[34:28]=7'b0110000;
	4'd4:led7s[34:28]=7'b0011001;
	4'd5:led7s[34:28]=7'b0010010;
	4'd6:led7s[34:28]=7'b0000010;
	4'd7:led7s[34:28]=7'b1111000;
	4'd8:led7s[34:28]=7'b0000000;
	4'd9:led7s[34:28]=7'b0010000;
	4'd10:led7s[34:28]=7'b0001000;
	4'd11:led7s[34:28]=7'b0000011;
	4'd12:led7s[34:28]=7'b1000110;
	4'd13:led7s[34:28]=7'b0100001;
	4'd14:led7s[34:28]=7'b0000110;
	4'd15:led7s[34:28]=7'b0001110;
	default:led7s[34:28]=7'bx;
	endcase
 end
always@(A_rbuf[23:20])
 begin
	case(A_rbuf[23:20])
	4'd0:led7s[41:35]=7'b1000000;
	4'd1:led7s[41:35]=7'b1111001;
	4'd2:led7s[41:35]=7'b0100100;
	4'd3:led7s[41:35]=7'b0110000;
	4'd4:led7s[41:35]=7'b0011001;
	4'd5:led7s[41:35]=7'b0010010;
	4'd6:led7s[41:35]=7'b0000010;
	4'd7:led7s[41:35]=7'b1111000;
	4'd8:led7s[41:35]=7'b0000000;
	4'd9:led7s[41:35]=7'b0010000;
	4'd10:led7s[41:35]=7'b0001000;
	4'd11:led7s[41:35]=7'b0000011;
	4'd12:led7s[41:35]=7'b1000110;
	4'd13:led7s[41:35]=7'b0100001;
	4'd14:led7s[41:35]=7'b0000110;
	4'd15:led7s[41:35]=7'b0001110;
	default:led7s[41:35]=7'bx;
	endcase
 end
always@(A_rbuf[27:24])
 begin
	case(A_rbuf[27:24])
	4'd0:led7s[48:42]=7'b1000000;
	4'd1:led7s[48:42]=7'b1111001;
	4'd2:led7s[48:42]=7'b0100100;
	4'd3:led7s[48:42]=7'b0110000;
	4'd4:led7s[48:42]=7'b0011001;
	4'd5:led7s[48:42]=7'b0010010;
	4'd6:led7s[48:42]=7'b0000010;
	4'd7:led7s[48:42]=7'b1111000;
	4'd8:led7s[48:42]=7'b0000000;
	4'd9:led7s[48:42]=7'b0010000;
	4'd10:led7s[48:42]=7'b0001000;
	4'd11:led7s[48:42]=7'b0000011;
	4'd12:led7s[48:42]=7'b1000110;
	4'd13:led7s[48:42]=7'b0100001;
	4'd14:led7s[48:42]=7'b0000110;
	4'd15:led7s[48:42]=7'b0001110;
	default:led7s[48:42]=7'bx;
	endcase
 end
always@(A_rbuf[31:28])
 begin
	case(A_rbuf[31:28])
	4'd0:led7s[55:49]=7'b1000000;
	4'd1:led7s[55:49]=7'b1111001;
	4'd2:led7s[55:49]=7'b0100100;
	4'd3:led7s[55:49]=7'b0110000;
	4'd4:led7s[55:49]=7'b0011001;
	4'd5:led7s[55:49]=7'b0010010;
	4'd6:led7s[55:49]=7'b0000010;
	4'd7:led7s[55:49]=7'b1111000;
	4'd8:led7s[55:49]=7'b0000000;
	4'd9:led7s[55:49]=7'b0010000;
	4'd10:led7s[55:49]=7'b0001000;
	4'd11:led7s[55:49]=7'b0000011;
	4'd12:led7s[55:49]=7'b1000110;
	4'd13:led7s[55:49]=7'b0100001;
	4'd14:led7s[55:49]=7'b0000110;
	4'd15:led7s[55:49]=7'b0001110;
	default:led7s[55:49]=7'bx;
	endcase
 end
endmodule