📄 fet140_ta_pwm05.c
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//*******************************************************************************
// MSP-FET430P140 Demo - Timer_A PWM TA1-2 up-downmode, 32kHz ACLK
//
// Description; This program will generate a two PWM outputs on P1.2/1.3 using
// Timer_A in an upmode. The value in CCR0, 128, defines the period/2 and the
// values in CCR1 and CCR1 the duty PWM cycles. Using 32kHz ACLK as TACLK,
// the timer period is 7.8ms with a 75% duty cycle on P1.2 and 25% on P1.3.
// As coded, the output signals TA1 on P1.2 and TA2 on P1.3 are inverted.
// ACLK = TACLK = LFXT1 = 32768, MCLK = default DCO ~ 800kHz.
// Normal mode LPM3
// //*External watch crystal installed on XIN XOUT is required for ACLK*//
//
// MSP430F149
// -----------------
// /|\| XIN|-
// | | | 32k
// --|RST XOUT|-
// | |
// | P1.2|--> CCR1 - 75% PWM
// | P1.3|--> CCR2 - 25% PWM
//
// M.Buccini
// Texas Instruments, Inc
// January 2002
// Built with IAR Embedded Workbench Version: 1.25A
//******************************************************************************
#include <msp430x14x.h>
void main(void)
{
WDTCTL = WDTPW +WDTHOLD; // Stop WDT
TACTL = TASSEL0 + TACLR; // ACLK, Clear Tar
CCR0 = 128; // PWM Period/2
CCTL1 = OUTMOD_2; // CCR1 reset/set
CCR1 = 64; // CCR1 PWM duty cycle
CCTL2 = OUTMOD_6; // CCR2 reset/set
CCR2 = 96; // CCR2 PWM duty cycle
P1DIR |= 0x0C; // P1.2 and P1.3 output
P1SEL |= 0x0C; // P1.2 and P1.3 TA1/2 otions
TACTL |= MC1 + MC0; // Start Timer_A in up-down mode
for (;;)
{
_BIS_SR(LPM3_bits); // Enter LPM3
_NOP(); // Required only for C-spy
}
}
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