prev_cmp_clock.qmsg

QuartusII编写的电子钟程序

{ "Info" "IOPT_OPT_PROTECT_A_CLOCK_MUX" "" "Info: Clock multiplexers have been protected" {  } {  } 0 0 "Clock multiplexers have been protected" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clock1:inst6\|jishiyujiaofen:inst\|mcount60:inst15\|74160:inst1\|9 data_in GND " "Warning (14130): Reduced register \"clock1:inst6\|jishiyujiaofen:inst\|mcount60:inst15\|74160:inst1\|9\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "alarm1:inst2\|jishiyujiaofenalarm:inst\|mcount60:inst15\|74160:inst1\|9 data_in GND " "Warning (14130): Reduced register \"alarm1:inst2\|jishiyujiaofenalarm:inst\|mcount60:inst15\|74160:inst1\|9\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clock1:inst6\|jishiyujiaofen:inst\|count60:inst12\|74160:inst1\|9 data_in GND " "Warning (14130): Reduced register \"clock1:inst6\|jishiyujiaofen:inst\|count60:inst12\|74160:inst1\|9\" with stuck data_in port to stuck value GND" {  } { { "74160.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IFTM_CARRY_SINGLE_TO_DOUBLE" "3 " "Info: Converted 3 single input CARRY primitives to CARRY_SUM primitives" {  } {  } 0 0 "Converted %1!d! single input CARRY primitives to CARRY_SUM primitives" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "music2:inst3\|music1:inst1\|div24:inst27\|div3:inst\|inst1 " "Info: Register \"music2:inst3\|music1:inst1\|div24:inst27\|div3:inst\|inst1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "music2:inst3\|music1:inst1\|div24:inst14\|div3:inst\|inst1 " "Info: Register \"music2:inst3\|music1:inst1\|div24:inst14\|div3:inst\|inst1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "music2:inst3\|music1:inst1\|div24:inst8\|div3:inst\|inst1 " "Info: Register \"music2:inst3\|music1:inst1\|div24:inst8\|div3:inst\|inst1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "256 " "Info: Implemented 256 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "233 " "Info: Implemented 233 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 20 18:02:07 2009 " "Info: Processing ended: Mon Apr 20 18:02:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 18:02:07 2009 " "Info: Processing started: Mon Apr 20 18:02:07 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "clock EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"clock\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "256 Top " "Info: Previous placement does not exist for 256 of 256 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "48mhz Global clock in PIN 28 " "Info: Automatically promoted signal \"48mhz\" to use Global clock in PIN 28" {  } { { "shumaxianshi.bdf" "" { Schematic "C:/Documents and Settings/as/桌面/很工整/clock/clock/shumaxianshi.bdf" { { 416 72 240 432 "48mhz" "" } { 144 32 80 160 "48mhz" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fenpin:inst\|div1000:inst1\|74160:inst1\|8 Global clock " "Info: Automatically promoted some destinations of signal \"fenpin:inst\|div1000:inst1\|74160:inst1\|8\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fenpin:inst\|div1000:inst1\|74160:inst1\|8 " "Info: Destination \"fenpin:inst\|div1000:inst1\|74160:inst1\|8\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "d:/altera/72/quartus/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "alarm1:inst2\|jishiyujiaofenalarm:inst\|inst " "Info: Destination \"alarm1:inst2\|jishiyujiaofenalarm:inst\|inst\" may be non-global or may not use global clock" {  } { { "jishiyujiaofenalarm.bdf" "" { Schematic "C:/Documents and Settings/as/桌面/很工整/clock/clock/jishiyujiaofenalarm.bdf" { { 64 336 400 112 "inst" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock1:inst6\|jishiyujiaofen:inst\|jiaofenshi:inst10\|inst6~4 " "Info: Destination \"clock1:inst6\|jishiyujiaofen:inst\|jiaofenshi:inst10\|inst6~4\" may be non-global or may not use global clock" {  } { { "jiaofenshi.bdf" "" { Schematic "C:/Documents and Settings/as/桌面/很工整/clock/clock/jiaofenshi.bdf" { { 56 296 360 104 "inst6" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "alarm1:inst2\|jishiyujiaofenalarm:inst\|inst1 " "Info: Destination \"alarm1:inst2\|jishiyujiaofenalarm:inst\|inst1\" may be non-global or may not use global clock" {  } { { "jishiyujiaofen