clock.tan.rpt

QuartusII编写的电子钟程序

; Clock Hold: '48mhz'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|7  ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|6 ; 48mhz      ; 48mhz    ; 158          ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                              ;                                                             ;            ;          ; 158          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------+-------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; 48mhz           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: '48mhz'                                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                ; To                                                                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 39.64 MHz ( period = 25.226 ns )                    ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|6         ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|9         ; 48mhz      ; 48mhz    ; None                        ; None                      ; 1.334 ns                ;
; N/A                                     ; 39.64 MHz ( period = 25.224 ns )                    ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|6         ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|8         ; 48mhz      ; 48mhz    ; None                        ; None                      ; 1.332 ns                ;
; N/A                                     ; 39.65 MHz ( period = 25.218 ns )                    ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|6         ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|7         ; 48mhz      ; 48mhz    ; None                        ; None                      ; 1.326 ns                ;
; N/A                                     ; 39.66 MHz ( period = 25.217 ns )                    ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|6         ; clock1:inst6|jishiyujiaofen:inst|xingqi:inst14|74160:inst|6         ; 48mhz      ; 48mhz    ; None                        ; None                      ; 1.325 ns                ;