display.vhd.bak

VHDL编写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity display is
	port(clk:in std_logic;  --1000Hz
		sec10,sec,secl:in std_logic_vector(3 downto 0);
		lsd:out std_logic_vector(2 downto 0);
		bcd:out std_logic_vector(3 downto 0);
		bcds:out std_logic);
end display;
architecture behav of display is
		signal cnt2:integer range 0 to 4;		
begin
	process(clk,sec10,sec,secl)
		begin
			if rising_edge(clk)then
				if cnt2=0 then
					bcds<='0';
					bcd<=sec10;
					lsd<="100";
					cnt2<=cnt2+1;
				elsif cnt2=1 then
					bcds<='0';
					bcd<=sec;
					lsd<="010";
					cnt2<=cnt2+1;
				elsif cnt2=2 then
					bcds<='1';
					bcd<=sec;
					lsd<="010";
					cnt2<=cnt2+1;
				elsif cnt2=3 then
					bcds<='0';
					bcd<=secl;
					lsd<="001";
					cnt2<=cnt2+1;
				elsif cnt2=4 then
					cnt2<=0;
				end if;
			end if;
	end process;
end behav;