or_gate.vhd

VHDL编写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or_gate is
	port(in1:in std_logic;
		 in2:in std_logic;
		 q:out std_logic);
end or_gate;
architecture behav of or_gate is
begin
	q<=in1 or in2;
end behav;