prev_cmp_watch.tan.qmsg

VHDL编写的

{ "Info" "ITDB_FULL_TCO_RESULT" "clk bell ctr:inst2\|bell_3 26.000 ns register " "Info: tco from clock \"clk\" to destination pin \"bell\" through register \"ctr:inst2\|bell_3\" is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns ctr:inst2\|clk1 2 REG LC50 53 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 53; REG Node = 'ctr:inst2\|clk1'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk ctr:inst2|clk1 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ctr:inst2\|bell_3 3 REG LC4 5 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC4; Fanout = 5; REG Node = 'ctr:inst2\|bell_3'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ctr:inst2|clk1 ctr:inst2|bell_3 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|bell_3 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|bell_3 {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctr:inst2\|bell_3 1 REG LC4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 5; REG Node = 'ctr:inst2\|bell_3'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctr:inst2|bell_3 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns ctr:inst2\|bell~4 2 COMB LC40 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC40; Fanout = 1; COMB Node = 'ctr:inst2\|bell~4'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { ctr:inst2|bell_3 ctr:inst2|bell~4 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns bell 3 PIN PIN_28 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'bell'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { ctr:inst2|bell~4 bell } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -72 280 456 -56 "bell" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 84.62 % ) " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { ctr:inst2|bell_3 ctr:inst2|bell~4 bell } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { ctr:inst2|bell_3 {} ctr:inst2|bell~4 {} bell {} } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|bell_3 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|bell_3 {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { ctr:inst2|bell_3 ctr:inst2|bell~4 bell } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { ctr:inst2|bell_3 {} ctr:inst2|bell~4 {} bell {} } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "keyboard:inst\|pre_state keyin\[0\] clk -3.000 ns register " "Info: th for register \"keyboard:inst\|pre_state\" (data pin = \"keyin\[0\]\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns keyboard:inst\|pre_state 2 REG LC94 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC94; Fanout = 11; REG Node = 'keyboard:inst\|pre_state'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk keyboard:inst|pre_state } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns keyin\[0\] 1 PIN PIN_54 11 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 11; PIN Node = 'keyin\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[0] } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { 128 56 72 298 "keyin\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns keyboard:inst\|pre_state 2 REG LC94 11 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 11; REG Node = 'keyboard:inst\|pre_state'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { keyin[0] keyboard:inst|pre_state } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { keyin[0] keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { keyin[0] {} keyin[0]~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { keyin[0] keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { keyin[0] {} keyin[0]~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Peak virtual memory: 120 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 11 03:09:24 2009 " "Info: Processing ended: Wed Mar 11 03:09:24 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}