prev_cmp_watch.tan.qmsg

VHDL编写的

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ctr:inst2\|cnt1 register ctr:inst2\|q2\[0\] 33.33 MHz 30.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 33.33 MHz between source register \"ctr:inst2\|cnt1\" and destination register \"ctr:inst2\|q2\[0\]\" (period= 30.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "25.000 ns + Longest register register " "Info: + Longest register to register delay is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctr:inst2\|cnt1 1 REG LC105 217 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC105; Fanout = 217; REG Node = 'ctr:inst2\|cnt1'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctr:inst2|cnt1 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns ctr:inst2\|q2~4463 2 COMB SEXP33 3 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP33; Fanout = 3; COMB Node = 'ctr:inst2\|q2~4463'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { ctr:inst2|cnt1 ctr:inst2|q2~4463 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 17.000 ns ctr:inst2\|q2~4469 3 COMB LC34 2 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 17.000 ns; Loc. = LC34; Fanout = 2; COMB Node = 'ctr:inst2\|q2~4469'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { ctr:inst2|q2~4463 ctr:inst2|q2~4469 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 25.000 ns ctr:inst2\|q2\[0\] 4 REG LC84 26 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 25.000 ns; Loc. = LC84; Fanout = 26; REG Node = 'ctr:inst2\|q2\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ctr:inst2|q2~4469 ctr:inst2|q2[0] } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns ( 84.00 % ) " "Info: Total cell delay = 21.000 ns ( 84.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 16.00 % ) " "Info: Total interconnect delay = 4.000 ns ( 16.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.000 ns" { ctr:inst2|cnt1 ctr:inst2|q2~4463 ctr:inst2|q2~4469 ctr:inst2|q2[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.000 ns" { ctr:inst2|cnt1 {} ctr:inst2|q2~4463 {} ctr:inst2|q2~4469 {} ctr:inst2|q2[0] {} } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 8.000ns 7.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns ctr:inst2\|clk1 2 REG LC50 53 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 53; REG Node = 'ctr:inst2\|clk1'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk ctr:inst2|clk1 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ctr:inst2\|q2\[0\] 3 REG LC84 26 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC84; Fanout = 26; REG Node = 'ctr:inst2\|q2\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ctr:inst2|clk1 ctr:inst2|q2[0] } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|q2[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|q2[0] {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns keyboard:inst\|cnt 2 REG LC90 1 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC90; Fanout = 1; REG Node = 'keyboard:inst\|cnt'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk keyboard:inst|cnt } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ctr:inst2\|cnt1 3 REG LC105 217 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC105; Fanout = 217; REG Node = 'ctr:inst2\|cnt1'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { keyboard:inst|cnt ctr:inst2|cnt1 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk keyboard:inst|cnt ctr:inst2|cnt1 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} keyboard:inst|cnt {} ctr:inst2|cnt1 {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|q2[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|q2[0] {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk keyboard:inst|cnt ctr:inst2|cnt1 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} keyboard:inst|cnt {} ctr:inst2|cnt1 {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 120 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.000 ns" { ctr:inst2|cnt1 ctr:inst2|q2~4463 ctr:inst2|q2~4469 ctr:inst2|q2[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.000 ns" { ctr:inst2|cnt1 {} ctr:inst2|q2~4463 {} ctr:inst2|q2~4469 {} ctr:inst2|q2[0] {} } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 8.000ns 7.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|q2[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|q2[0] {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk keyboard:inst|cnt ctr:inst2|cnt1 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} keyboard:inst|cnt {} ctr:inst2|cnt1 {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "keyboard:inst\|reset ctr:inst2\|q3\[0\] clk 4.0 ns " "Info: Found hold time violation between source  pin or register \"keyboard:inst\|reset\" and destination pin or register \"ctr:inst2\|q3\[0\]\" for clock \"clk\" (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.000 ns + Largest " "Info: + Largest clock skew is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns ctr:inst2\|clk1 2 REG LC50 53 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 53; REG Node = 'ctr:inst2\|clk1'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk ctr:inst2|clk1 } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ctr:inst2\|q3\[0\] 3 REG LC114 41 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC114; Fanout = 41; REG Node = 'ctr:inst2\|q3\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { ctr:inst2|clk1 ctr:inst2|q3[0] } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|q3[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|q3[0] {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns keyboard:inst\|reset 2 REG LC82 56 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC82; Fanout = 56; REG Node = 'keyboard:inst\|reset'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk keyboard:inst|reset } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|reset } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|reset {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|q3[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|q3[0] {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|reset } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|reset {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyboard:inst\|reset 1 REG LC82 56 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC82; Fanout = 56; REG Node = 'keyboard:inst\|reset'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyboard:inst|reset } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns ctr:inst2\|q3\[0\] 2 REG LC114 41 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC114; Fanout = 41; REG Node = 'ctr:inst2\|q3\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { keyboard:inst|reset ctr:inst2|q3[0] } "NODE_NAME" } } { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { keyboard:inst|reset ctr:inst2|q3[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { keyboard:inst|reset {} ctr:inst2|q3[0] {} } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "ctr.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/ctr.vhd" 120 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk ctr:inst2|clk1 ctr:inst2|q3[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk {} clk~out {} ctr:inst2|clk1 {} ctr:inst2|q3[0] {} } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|reset } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|reset {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { keyboard:inst|reset ctr:inst2|q3[0] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "8.000 ns" { keyboard:inst|reset {} ctr:inst2|q3[0] {} } { 0.000ns 2.000ns } { 0.000ns 6.000ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "keyboard:inst\|pre_state keyin\[0\] clk 11.000 ns register " "Info: tsu for register \"keyboard:inst\|pre_state\" (data pin = \"keyin\[0\]\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns keyin\[0\] 1 PIN PIN_54 11 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 11; PIN Node = 'keyin\[0\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[0] } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { 128 56 72 298 "keyin\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns keyboard:inst\|pre_state 2 REG LC94 11 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC94; Fanout = 11; REG Node = 'keyboard:inst\|pre_state'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { keyin[0] keyboard:inst|pre_state } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { keyin[0] keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { keyin[0] {} keyin[0]~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/watch.bdf" { { -64 96 264 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns keyboard:inst\|pre_state 2 REG LC94 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC94; Fanout = 11; REG Node = 'keyboard:inst\|pre_state'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk keyboard:inst|pre_state } "NODE_NAME" } } { "keyboard.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/数字系统设计/th最新版修改/keyboard.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { keyin[0] keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { keyin[0] {} keyin[0]~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk keyboard:inst|pre_state } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk {} clk~out {} keyboard:inst|pre_state {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}